e014068.PDF

AUD IO

96 kHz Sampling

Rate Converter

for high-end digital audio

Design by T. Giesberts

This converter is speciﬁcally intended to upgrade somewhat dated, dig-

ital signal sources. It recognises all common sampling rates and converts

these to 96 kHz. By design, this converter is ideally suited to be com-

bined with our ‘Audio DAC 2000’. However, it may also be used as a

stand-alone unit.

Elektor Electronics

4/2001

AUD IO

by most readers as a signiﬁcant feature. This

requires no further debate.

However, a question that will be asked by

some is: what is the sense in preceding a D/A

converter by a 96-kHz-up-sampling-converter

when the actual signal sources under con-

sideration do not use a higher sampling rate

than 44.1 kHz (CD) or 48 kHz (DAT)?

In the first instance this appears to be a

valid argument indeed, but up-sampling has,

in this case, real advantages. Of course, by

converting from 44.1 to 96 kHz no additional

information is gained from the CD. However,

the increased number of steps creates an

‘intelligent’ rounding of the original steps.

Consequently, the digital signal has

increased resolution with the result that the

D/A-converter can better process this signal

without the need for very steep ﬁlters.

The result is a measurable ‘cleaner’ signal

that also, according to the true audio fanatic,

clearly sounds better. Whether everyone will

hear the difference is questionable but it is

obvious that up-sampling deserves the ben-

eﬁt of the doubt.

Specifications

– stand-alone

– 24 bit I/O

– 32 kHz to 96 kHz input sampling-rate range

(8 kHz to 108 kHz using external OMCK)

– 1:3 and 3:1 sampling-rate ratio between in- and output possible

– 128 dB dynamic range

– THD+N > 117 dB

– 2 S-output (alternative receiver for Audio DAC 2000 )

– coaxial input

– optical input

– two coaxial outputs

– optical output

– choice of Master or Slave mode

Quality conscious audiophiles have,

in all likelihood, already replaced the

standard D/A-converter in their

equipment with an up-to-date 24-

bit/96-kHz model, such as the ‘Audio

DAC 2000’, published in the Novem-

ber and December 1999 issues of

Elektor Electronics . The next logical

step is to upgrade the audio instal-

lation so that the sampling rate of

the (digital) signal sources is con-

verted to 96 kHz before presenting it

to the D/A-converter.

The up-sampling converter

described here makes this possible.

It accepts all imaginable sampling

frequencies and has been designed

in such a way to allow it to be used

in three different ways. If there is

sufficient space inside the enclosure

it may, for example, be built into an

existing CD player. Alternatively, it

may be ﬁtted into its own enclosure

and used as a stand-alone device.

Alternatively, it can be combined

with the ‘Audio-DAC 2000’ by simply

substituting it for the receiver sec-

tion. The latter has the added advan-

tage of not requiring an additional

power supply since this may be

obtained automatically from the

Audio-DAC.

The heart

The converter presented here consists essen-

tially of a single IC: the integrated sample

rate converter plus AES3 tranceiver type

CS8420 from Crystal. This IC is intended for

16-, 20- and 24-bit applications where the

input sample rate is unknown or clearly asyn-

chronous with the desired sampling rate. The

overall functioning of the IC relies on the con-

version of the input sample rate to a very high

frequency, which is subsequently divided to

obtain the required value. This value is

deﬁned by the frequency of the master clock

input.

At the input of the CS8420 there is the

choice of AES3 or three wire serial format. At

the output, both formats are available. The

control of the data stream between input and

output may be controlled with an external

microcontroller. However, it is also possible

to do without such a controller by using one

of the six hardware modes built into the IC.

In our case the CS8420 is used in hardware

mode 1a. Figure 1 shows the internal block

diagram when the IC is in this mode. As can

be observed, the AES3-receiver (RXP/RXN)

has been utilised here and the converted sig-

nal is fed to both an AES3-encoder and a ser-

ial audio port.

The various pins of the CS8420 have dif-

ferent functions and names depending on the

hardware mode. To avoid confusion, only

those pins that have a function and designa-

tion related to hardware mode 1a are shown

on the complete schematic for the up-sam-

Sense or nonsense?

The fact that the combination of up-

sampling-converter and Audio DAC

results in a very universal D/A-con-

verter that can deal with all common

sampling rates will be appreciated

VD+

Output

Clock

Source

OMCK

DFC0

DFC1

S/AES

H/S

Clocked by

Input Derived Clock

Clocked by

Output Clock

Serial

Audio

Output

OLRCK

OSCLK

SDOUT

AES3 Rx

Deco d er

Sample

Rate

Converter

RXP

RXN

AES3

Encoder

& Tx

TXP

TXN

C & U Data Buffer

TCBLD

RMCK

RERR

MUTE

PRO/C

COPY

ORIG

EMPH/U

AUDIO/V

TCBL

010014 - 12

Figure 1. Block diagram of the CS8420 in hardware mode 1a.

4/2001

Elektor Electronics

AUD IO

+5V

zie tekst

* see text

* siehe Text

* voir texte

R13

IC3

IC2

+5VA

+5V

TOTX173

TORX173

47µH

R14

8k2

C10

C11

C16

100n

1µ

50V

100n

1µ

50V

100n

+5V

JP1

R16

75 Ω

JP2

VA+

VD+

opto

coax

PRO/C

H/S

TR1

R15

10n

TCBL

TCBLD

S/PDIF

RXP

TXP

TXN

IC1

RXN

C17

FILT

SDOUT

OLRCK

OSCLK

47n

AUDIO/V

RST

R18

75 Ω

OMCK

10n

2n2

CS8420

EMPH/U

82n

R17

ORIG

RERR

20 : 2 : 2

IC5.F

COPY

RMCK

+5V

R23

MUTE

DFC0

DFC1

C18

S/AES

ORIGINAL

47n

AGND

DGND

IC5.E

+5V

R22

IC5.C

COPY

IC5.B

R21

IC5.D

K5/DF1704

Audio-

+5V

ERROR

MUTE

DEM

RST

DAC2000

C19

IC5.A

47 Ω

100n

R10

47 Ω

R19

R11

47 Ω

IC4 = 74HCU04

IC5 = 74HC14

+5V

R12

47 Ω

IC4.F

IC4.E

IC4.D

IC4.B

IC4.C

R20

+5VA

+5V

IC4.A

JP3

C23

10µH

2 Ω 2

C22

100p

Ext. OMCK

27p

C24

C25

C12

C13

C14

C15

IC4

IC5

C21

C20

24,576MHz

100µ

10V

100n

100µ

10V

100n

100µ

10V

100n

5V6

1W3

33p

TR2

C33

C30

IC6

R25

1 Ω 5

7805

4VA5

R24

C32

C31

D 5

C29

C27

C28

C26

32mA T

B80C1500

1000µ

25V

100n

10µ

63V

100n

C30...C33 = 4x 22n

POWER

010014 - 11

Figure 2. With the exception of the CS8420 the converter hardly consists of any active components.

pling converter. Those of you who would like

to know more about the IC, or are curious

about the other modes, are referred to the

datasheet for the IC and application note

AN159 available from the manufacturer’s web

site at http://www.cirrus.com .

obvious that the amount of hardware

required is within reason.

idea of using a real switch was

rejected because this selection is

normally made only once.

The PLL on the input of the

CS8420 has an external filter net-

work (C3/C4/R2/R3) that may be

modified for other frequencies, if

desired (refer to the application note

for details). The values shown in the

schematic give the network a fre-

quency range from 32 kHz to 96 kHz

(R3 is not ﬁtted).

Inputs and outputs

This circuit permits the input signal

to take the form of either a coaxial

signal (K1) or an optical signal (IC2).

The latter is a standard optical

Toslink receiver module that we

have used on previous occasions.

The selection is made by the appro-

priate location of jumper JP1. The

The complete schematic

The practical schematic of the up-sampling

converter is shown in Figure 2 . It is quite

clearly laid out and makes it immediately

Elektor Electronics

4/2001

AUD IO

The AES3-outputs are routed via

a wind-your-own transformer to two

(electrically isolated) coaxial outputs.

The output grounds are decoupled

with C17 and C18 to suppress RF

interference.

In addition, an optical output is

provided by IC3. Its input signal

comes from the symmetric output

(TXP).

The serial audio output port

(SDOUT/OLRCK/OSCLK/OMCK) is

used, via K4, to route the correct sig-

nals to the ‘Audio-DAC 2000’. For this

purpose, K4 is connected with a 16-

way ribbon cable to K5 on the DAC

PCB. The double bandwidth (DBW)

feature is than always active and the

Bessel ﬁlter in the ‘Audio-DAC 2000’

is activated.

The mute function is derived, via

inverter IC5c, from the receiver-error-

indicator (RERR). Several channel-

status-bits are also connected to the

output pins. One of these is the

emphasis bit that signals the Audio-

DAC via IC5d whether pre-emphasis

(50/15 µs) has been applied or not.

The reset signal is the same as

the one for the CS8420, which is gen-

erated by the circuit consisting of

R19-C19-IC5a. The format of the dig-

ital audio output port is I 2 S-compat-

ible. Therefore, digital filter DF1704

has to be conﬁgured for this format.

Some Test Results

A few measurements have been

performed in the digital domain

with the help of special measuring

equipment

(‘CDBCapture+board’) that

clearly show what the up-sampling

converter does.

FREQUENCY DOMAIN

-20

-40

-60

-80

-100

-120

-140

Figure A shows the output of a

DVD player with a 24 bit, 1 kHz

test signal at a sampling rate of

96 kHz. This signal is passed

through the converter and the

result is shown in Figure B . The

only visible irregularities are a few

(non-harmonic) frequency compo-

nents which are probably the

result of the up-down-sampling

process and added dither. The lat-

ter explains also why the noise

ﬂoor is a little higher. The signal to

noise ratio of this signal (measured

digitally!) amounts to 120 dB. This

is much lower than is possible with

a 24-bit-D/A-converter (physical

limit, noise, etc.)

-160

-180

-200

-220

-240

5000

10000

15000

20000

25000

30000

35000

40000

48000

Frequency

010014 - A

FREQUENCY DOMAIN

-20

-40

-60

-80

-100

-120

-140

-160

-180

Figure C shows the result of a

typical application. The 1 kHz sig-

nal from the test CD with a sam-

pling frequency of 44.1kHz is now

increased to a sampling frequency

of 96 kHz. It is clearly visible that

the noise ﬂoor is considerably

higher with a 16-bit signal and that

the bandwidth is limited to

22.05 kHz (by the converter). The

mixing products of the original

sampling frequency have now

become visible because of 24-bit

resolution. These will disappear

completely in the noise at the D/A-

conversion stage. The signal to

noise ratio is a little more that

98 dB, the exact same value as

measured at the digital output of a

CD-player.

-200

-220

5000

10000

15000

20000

25000

30000

35000

40000

48000

Frequency

010014 - B

FREQUENCY DOMAIN

-20

-40

Master-clock

The frequency of the OMCK signal

deﬁnes the output sample rate with

the condition that the sample rate is

smaller by a ratio of 256 compared to

OMCK. To obtain 96 kHz a master-

clock of 24.576 MHz is necessary.

The required clock generator is con-

structed around IC4a and X1. Pay

careful attention to the C load of the

crystal used, because this has to be

equal to C20/2 (where C20 = C21).

C22 compensates the propagation

delay of buffer IC4a and has to

approximately equal to C load .

The crystal has to be cut for fun-

damental frequency and parallel res-

onance. Commonly available crystals

are intended for series resonance. If

a series resonance crystal is used

the oscillator may run at the wrong

frequency, or not work at all. There is

also the possibility that the crystal is

designed for parallel resonance but

has been cut for 3 rd harmonic reso-

nance (a.k.a. third overtone). To

-60

-80

-100

-120

-140

-160

-180

-200

-220

5000

10000

15000

20000

25000

30000

35000

40000

48000

Frequency

010014 - C

adapt the oscillator to a crystal of

this type it is necessary to fit an

additional inductor (L4), which,

together with C22, is tuned to a fre-

quency just below the harmonic in

order to suppress the fundamental.

L4 will typically have a value of 1.5

or 1.8 µH, but it may be necessary to

experiment a little with this.

As an additional feature, JP3 pro-

vides for the possibility to supply

OMCK from an external oscillator

(input ‘Ext.OMCK’). This makes any

frequency between 8 kHz and 108 kHz possi-

ble, provided, the ratio of the input sample

rate and the output sample rate is between

1:3 and 3:1. C20…C22, X1 and L4 have to be

removed in this case. And don’t forget to ﬁt a

jumper on the pins of JP3, of course!

Adjustments

Four pins deﬁne the operating mode of the IC:

hardware mode is selected by making H/S

‘high’. The state of DFC0, DFC1 and S/AES

further define which one of six hardware

modes is chosen.

4/2001

Elektor Electronics

AUD IO

R24

C26

IC6

C28

C30

R12

R11

R10

R22

R23

R21

C21

IC4

TR1

C16

C11

R13

R14

R16

R17

R18

R15

OUT1

IC3

IC2

Figure 3. The PCB for the converter is double sided.

The (single sided) power supply may be separated with the aid

of a saw.

Elektor Electronics

4/2001

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