at5-ev-0105.pdf

AT3 BLOCK DIAGRAM

04-- 0402 footprint

06-- 0603 footprint

08-- 0805 footprint

12-- 1206 footprint

F-- 1% tolerance

PCB STACK UP

LAYER 1 : TOP

LAYER 2 : SGND1

CPU THERMAL

SENSOR

CPU

Merom

LAYER 3 : IN1

14.318MHz

PAG 5

LAYER 4 : IN2

478P (uPGA)/35W

PAG 3,4

CLK_CPU_BCLK,CLK_CPU_BCLK#

CLK_MCH_BCLK,CLK_MCH_BCLK#

DREFCLK,DREFCLK#

DREFSSCLK,DREFSSCLK#

LAYER 5 : VCC

CLOCK GEN

LAYER 6 : IN3

ICS9LPRS355AGLFT

64pinsTSSOP

LAYER 7 : SGND2

PAG 2

LAYER 8 : BOT

Option for 17" only

NVDIA G3-64 for 15.4"

PCI-Express 16X

NVDIA G3-128 for 17"

HDMI CON

DDRII-SODIMM1

820p FCBGA

PAG

15,16,17,18,19,20

PAG 26

DDRII 533,667 MHz

NORTH BRIDGE

TV_OUT

PAG 13,14

Cable

Docking

VGA

Crestline

TV_OUT

RJ-45

CIR/Pwr btn

SPDIF Out

Stereo MIC

Headphone Jack

DDRII-SODIMM2

DDRII 533,667 MHz

CRT/S-VIDEO

CRT_OUT

PAG 25

PAG 13,14

PAG

7,8,9,10,11,12

LVDS(2 Channel)

Panel Connector

15" / 17"

PAG 26

NBSRCCLK, NBSRCCLK#

USB Port

VOL Cntr

DMI LINK

PAG 38

USB2.0

Option for 17" only

0,1,2

4,6,7

SYSTEM CHARGER(MAX8724)

SATA2

Bluetooth

USB2.0 I/O Ports

Camera

Mini PCI-E Card x1

Express Card x1

Cable Docking x1

SATA - HDD

PAG 41

PAG 35

PAG 32

PAG 35

SOUTH BRIDGE

PCI BUS / 33MHz

SYSTEM POWER MAX8778

SATA0 150MB

PAG 42

PCI-E

SATA - HDD

ICH-8M

PAG 32

DDR II SMDDR_VTERM

1.8V/1.8VSUS(TPS51116REGR)

PAG 46

Azalia

(66/100/133)

PATA

PAG 21,22,23,24

PATA-

CD-ROM

Mini PCI-E

Card

LAN

Express

Card

(NEW CARD)

RICOH

PAG 32

Realtek

PCIE-LAN

RICOH 832

PCI Express

Mini Card

Realtek

VCCP +1.5V AND GMCH

1.05V(MAX8717)

RTL8101E/8111B

(Wireless

LAN/WAN)

Two-element

microphone

LPC

ALC 268

(10/100/GagaLAN)

PAG 27,28

PAG 43

PAG 39

PAG 33,34

PAG 35

PAG 29

Keyboard

VGACORE(1.025V)MAX1992

Touch Pad

PAG 36

ENE KBC

Audio Jacks

Memory

CardReader

IEEE1394

CONN

PAG 45

(Phone/ MIC)

RJ45

KB3920 Bx

SIM CARD

PAG 29

CIR

PAG 36

KB3926 Bx

PAG 28

PAG 27

PAG 32

PAG 33

CPU CORE MAX8771

PAG 44

Capacitive Sense

PAG 37,48

PCI ROUTING

TABLE

PAG 36

AUDIO

Amplifier

MDC DAA

IDSEL

INTERUPT

DEVICE

SI3080

REQ0# / GNT0#

AD25

INTE#,INTF#

RICOH832

PAG 30

PAG 31

REQ1# / GNT1#

AD22

INTC#,INTD#

MINI PCI for debug

PROJECT : AT3

FAN

Flash

SPI

Jack to

Speaker

MODEM RJ 11

Quanta Computer Inc.

PAG 38

PAG 37

PAG 30

PAG 33

Size

Document Number

Rev

Custom

BLOCK DIAGRAM

NB5/RD1/HW2

Date:

Thursday, January 11, 2007

Sheet

+3V

L42

BLM21PG600SN1D/08

CLK_3GPLLREQ#

R321

10K/04

+CK_VDD_MAIN

NEW-CARD_CLK_REQ#

R322

10K/04

120 ohms@100Mhz

C400

22U/10V/12

C464

.1U/10V/04

C436

.1U/10V/04

C441

.1U/10V/04

C446

.1U/10V/04

C429

.1U/10V/04

SI-2 change

SI-1 modify

( remove

R256 --not

need )

CG_XOUT

L43

BLM21PG600SN1D/08

CG_XIN

VDDCPU

14.318MHZ

C431

27P/50V/04

C430

27P/50V/04

internal have

already build-in

33ohm damping

resisteor

C447

22U/10V/12

C445

.1U/10V/04

14.318MHz

L44

BLM21PG600SN1D/08

RP40

4P2R-S-0

U16

CLK_CPU_BCLK

+CK_VDD_MAIN2

CLK_CPU_BCLK#

120 ohms@100Mhz

+CK_VDD_MAIN

RHCLK_CPU

RP41

4P2R-S-0

CLK_MCH_BCLK

VDDPLL3

CPUCLKT0

RHCLK_CPU#

VDD48

CPUCLKC0

CLK_MCH_BCLK#

C479

22U/10V/12

C456

.1U/10V/04

C473

.1U/10V/04

C448

.1U/10V/04

C462

.1U/10V/04

C458

.1U/10V/04

C452

.1U/10V/04

CK505

VDDPCI

R HCLK_MCH

RP45

*4P2R-S-0

CLK_CPU_ITP

VDDREF

CPUCLKT1

RHCLK_MCH#

CLK_CPU_ITP#

VDDSRC

VDDCPU

CPUCLKC1

VDDCPU

C PU_ITP

RP64

4P2R-S-0

CPUT2_ITP/SRCT8

CLK_PCIE_MINI_C

+CK_VDD_MAIN2

C PU_ITP#

SI-2 Add

VDD96I/O

CPUT2_ITP/SRCC8

CLK_PCIE_MINI_C#

VDDPLL3I/O

+3V

R_DOT96

RP42

4P2R-S-0

VDDSRCI/O

VDDCPU_IO

DOTT_96/SRCT0

DOTC_96/SRCC0

DREFCLK

R _DOT96#

DREFCLK#

SI-1 modify

( add in

UMA BOM )

+3V

R_DREFSSCLK

RP43

4P2R-S-0

DREFSSCLK

27MHz_Nonss/SRCCLK1/SE1

R_DREFSSCLK#

27Mhz_ss/SRCCLC1/SE2

DREFSSCLK#

R259

10K/04

SI-2 add -- reserve not need

R SRC_SATA

RSRC_SATA#

RP46

4P2R-S-0

SRCCLKT2/SATACL

SRCCLKC2/SATACL

SRCCLKT3/CR#_C

SRCCLKC3/CR#_D

SRCCLKT4

SRCCLKC4

PCI_STOP#

CPU_STOP#

SRCCLKT6

SRCCLKC6

SRCCLKT7/CR#_F

SRCCLKC7/CR#_E

SRCCLKT9

SRCCLKC9

SRCCLKT10

SRCCLKC10

SRCCLKT11/CR#_H

SRCCLKC11/CR#_G

CLK_PCIE_SATA 21

CLK_PCIE_SATA# 21

CG_XIN

Q16

2N7002E

R288

10K/06

R308

10K/06

CG_XOUT

R _CLK_PCIE_VGA

RP48

4P2R-S-0

CLK_PCIE_VGA

PCLK_MINI_LPC

R _CLK_PCIE_VGA#

CLK_PCIE_VGA#

CGDAT_SMB

R845

*100K/04

RSRC1_LAN

RSRC1_LAN#

RP50

4P2R-S-0

23,35

PDAT_SMB

CLK_PCIE_LAN

CLK_PCIE_LAN#

R269

*4.7K/04

PM_STPPCI#

CK_PWG

PM_STPPCI# 23

CK_PWRGD/PD#

FSLB/TEST_MODE

CLK_BSEL1

R298

4.7K/04

FSB

PM_STPCPU#

PM_STPCPU# 23

+3V

R SRC_ICH

RP49

4P2R-S-0

CLK_PCIE_ICH

Q17

2N7002E

RSRC_ICH#

CLK_PCIE_ICH#

CGCLK_SMB

C LK_PCIE_MINI_

RP47

4P2R-S-0

SCLK

SDATA

CLK_PCIE_MINI

13,14,39

CGCLK_SMB

0=overclocking

of CPU and

SRC Allowed

1 = overclocking

of CPU and SRC

not Allowed

CGCLK_SMB

CGDAT_SMB

C LK_PCIE_MINI_#

23,35

PCLK_SMB

CLK_PCIE_MINI#

13,14,39

CGDAT_SMB

RSRC_MCH

RP52

4P2R-S-0

CLK_PCIE_3GPLL 7

CLK_PCIE_3GPLL# 7

RSRC_MCH#

GND

GND48

GNDCPU

GNDPCI

GNDREF

GNDSRC

CLK_PCIE_NEW

RP51

4P2R-S-0

CLK_PCIE_NEW_C

CLK_PCIE_NEW#

CLK_PCIE_NEW_C#

N EW-CARD_CLK_REQ#_R

CLK_3GPLLREQ#_R

R324

475/F/03

NEW-CARD_CLK_REQ#

R323

475/F/03

CLK_3GPLLREQ#

CLK_3GPLLREQ# 7

+3V

R_PCLK_KB3920

R250

33/04

PCICLK0/CR#_A

PCICLK1/CR#_B

PCICLK2/TME

PCICLK3

PCICLK4/27_SELECT

PCLK_LPC_KB3920 37,48

C416

*33P/50V/04

PCLK_LPC_KB3920

R_PCLK_5C832

R260

33/04

PCI_CLK_5C832

PCLK_MINI_LPC

PCI_ICH

R279

33/04

PCLK_LPC_DEBUG

C421

*33P/50V/04

PCI_CLK_5C832

PCLK_ICH

PCLK_LPC_DEBUG

14M_ICH

T258

FCTSEL1

R293

33/04

form ICS FAE

recommend(defaule is

Hi )

PCLK_MINI

C442

*33P/50V/04

SI-1 modify for

S3 resume issue

R287

*10K/04

C438

*33P/50V/04

ITP_EN

R285

33/04

PCI_F5/ITP_EN

USB_48MHZ/FSLA

FSLC/TST_SL/REF

PCLK_ICH

FCTSEL1

C432

*33P/50V/04

R292

33/04

CLKUSB_48 23

CLK_BSEL0

FSA

R295

4.7K/04

FSC

R257

4.7K/04

CLK_BSEL2

for EMI

R266

33/04

14M_ICH

R296

10K/04

ICS9LPRS355AGLFT/CY28548ZXCT/RTM875T-606

GCLK_SEL = FCTSEL1

FCTSEL1

(PIN13)

CPU Clock select

FSC

FSB

FSA

CPU

SRC

PCI

0=UMA

PIN20

PIN21

PIN24

PIN25

100

1 = External VGA

R309

0/04

CLK_BSEL0

R310

0/04

CPU_BSEL0

MCH_BSEL0 7

133

R307

*56/04

+1.05V

0=UMA

DOT96T

DOT96C

SRCT1/LCDT_100

166

200

266

333

400

R301

1K/04

+3V

1 = External

VGA

R305

0/04

CLK_BSEL1

R299

0/04

CPU_BSEL1

MCH_BSEL1 7

SRCT0

SRCC0

27Mout-NSS

27Mout-SS

100

Enable ITP

R302

*0/04

100

*10K/04

R303

1K/04

+1.05V

R283

R277

0/04

CLK_BSEL2

R258

0/04

CPU_BSEL2

MCH_BSEL2 7

RSVD

ITP_EN

R264

*0/04

<FAE>

1K to NB only when

XDP is implement.No

XDP can use 0 ohm

R265

1K/04

+1.05V

PROJECT : AT3

10K/04

Quanta Computer Inc.

R825

Size

Document Number

Rev

Custom

CLOCK GENERATOR

NB5/RD1/HW2

Date:

Thursday, January 11, 2007

Sheet

H_A#[3..16]

U31A

H_D#[0..63]

U31B

H_D#[0..63]

H_A#[3..16]

H_D#[0..63]

H_A#3

H_D#0

H_D#32

E22

F24

Y22

AB24

V24

V26

V23

T22

U25

U23

A[3]#

ADS#

H_ADS#

D[0]#

D[1]#

D[32]#

D[33]#

D[34]#

D[35]#

D[36]#

D[37]#

D[38]#

D[39]#

H_A#4

H_D#1

H_D#33

A[4]#

A[5]#

A[6]#

A[7]#

A[8]#

A[9]#

BNR#

H_BNR#

H_A#5

H_D#2

H_D#34

E26

BPRI#

H_BPRI#

D[2]#

H_A#6

C926*100P/50V/04

H_D#3

H_D#35

H_D#37

G22

D[3]#

H_A#7

H_D#4

H_D#36

F21

F23

H_DEFER#

DEFER#

DRDY#

D[4]#

H_A#8

H_D#5

G25

H_DRDY#

D[5]#

H_A#9

H_D#6

H_D#38

SI-2 modified

resevved for power

noise

E25

DBSY#

H_DBSY#

D[6]#

H_A#10

H_A#12

H_D#7

H_D#39

E23

K24

G24

A[10]#

A[11]#

A[12]#

A[13]#

A[14]#

A[15]#

A[16]#

D[7]#

D[8]#

D[9]#

H_A#11

H_D#8

H_D#10

H_D#40

Y25

W22

Y23

W24

W25

AA23

AA24

AB25

H_BR0#

BR0#

D[40]#

D[41]#

D[42]#

D[43]#

D[44]#

D[45]#

D[46]#

D[47]#

R167

56/04

H_D#9

H_D#41

H_A#13

H_IERR#

H_D#42

D20

J24

J23

H22

F26

K22

H23

+1.05V

IERR#

D[10]#

D[11]#

D[12]#

D[13]#

D[14]#

D[15]#

H_A#14

H_A#16

H_D#11

H_D#43

H_D#44

INIT#

H_INIT#

H_A#15

C927*100P/50V/04

H_D#12

H_D#13

H_D#45

LOCK#

H_LOCK#

H_D#14

H_D#46

H_ADSTB#0

ADSTB[0]#

H_REQ#[0..4]

H_RESET#

H_D#15

H_D#47

H_REQ#[0..4]

H_RESET#

RESET#

RS[0]#

RS[1]#

RS[2]#

H_REQ#0

J26

Y26

H_RS#0

H_DSTBN#0

H_DSTBN#2

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

REQ[4]#

DSTBN[0]#

DSTBN[2]#

H_REQ#1

H26

AA26

H_RS#1

H_DSTBP#0

DSTBP[0]#

DSTBP[2]#

H_DSTBP#2

H_REQ#2

H25

U22

H_RS#2

H_DINV#0

DINV[0]#

DINV[2]#

H_DINV#2

H_REQ#3

TRDY#

H_TRDY#

H_REQ#4

H_D#[0..63]

H_A#[17..35]

H_D#16

H_D#48

N22

K25

P26

R23

AE24

AD24

H_A#[17..35]

H_HIT#

HIT#

HITM#

D[16]#

D[17]#

D[18]#

D[19]#

D[48]#

D[49]#

H_A#17

H_D#17

H_D#49

+1.05V

A[17]#

A[18]#

A[19]#

A[20]#

A[21]#

A[22]#

A[23]#

A[24]#

A[25]#

A[26]#

A[27]#

A[28]#

A[29]#

H_HITM#

H_A#18

H_D#18

H_D#50

AA21

AB22

AB21

AC26

AD20

AE22

AF23

AC25

AE21

AD21

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

H_A#19

ITP_BPM#0

H_D#19

H_D#51

H_D#52

SI-2

modified

for fix

run TAT

hang

AD4

AD3

AD1

AC4

BPM[0]#

BPM[1]#

BPM[2]#

BPM[3]#

H_A#20

ITP_BPM#1

Layout Note:

Place voltage

divider within

0.5" of GTLREF

H_D#20

H_D#21

L23

M24

L22

M23

P25

P23

P22

T24

R24

L25

D[20]#

D[21]#

D[22]#

D[23]#

D[24]#

D[25]#

D[26]#

D[27]#

D[28]#

D[29]#

H_A#21

ITP_BPM#2

ITP_BPM#4

H_D#53

R822

*56/04

H_A#22

ITP_BPM#3

H_D#22

H_D#54

H_A#23

AC2

AC1

H_D#23

H_D#55

PRDY#

PREQ#

H_A#24

ITP_BPM#5

H_D#24

H_D#56

H_A#25

H_A#26

ITP_TCK

H_D#25

H_D#57

H_D#59

H_PWRGD

AC5

AA6

AB3

TCK

TDI

TDO

ITP_TDI

H_D#26

H_D#58

H_A#27

ITP_TDO

H_D#27

C908

100P/50V/04

H_A#28

AB5

ITP_TMS

+1.05V

H_D#28

AC22

AD23

AF22

AC23

H_D#60

TMS

D[60]#

D[61]#

D[62]#

D[63]#

H_A#29

ITP_TRST#

H_D#29

H_D#61

AB6

TRST#

H_A#30

ITP_DBRESET#

H_D#30

H_D#62

C20

T25

N25

A[30]#

A[31]#

DBR#

SYS_RST#

D[30]#

D[31]#

H_A#31

H_A#32

H_A#33

H_A#34

H_A#35

H_D#31

H_D#63

R166

75/04

R151

1K/F/04

AA4

AB2

AA3

L26

AE25

H_DSTBN#1

H_DSTBN#3

A[32]#

A[33]#

A[34]#

A[35]#

DSTBN[1]#

DSTBN[3]#

THERMAL

M26

AF24

+1.05V

H_DSTBP#1

H_DSTBP#3

DSTBP[1]#

DSTBP[3]#

N24

AC20

H_DINV#1

H_DINV#3

DINV[1]#

DINV[3]#

CPU_PROCHOT#

D21

PROCHOT#

H_THERMDA

H_THERMDC

V_CPU_GTLREF

CPU_TEST1

CPU_TEST3

CPU_TEST4

CPU_TEST5

CPU_TEST6

COMP0

Note:

H_DPRTSTP need to daisy chain

from ICH8 to IMVP6 to CPU.

A24

B25

AD26

R26

U26

AA1

H_ADSTB#1

ADSTB[1]#

THERMDA

THERMDC

H_THERMDA

GTLREF

COMP[0]

COMP[1]

COMP[2]

COMP[3]

COMP1

C23

MISC

H_THERMDC

TEST1

CPU_TEST2

COMP2

D25

AF26

A26

H_A20M#

A20M#

TEST2

TEST4

TEST6

PM_THRMTRIP#

COMP3

C24

H_FERR#

PM_THRMTRIP# 7,21

FERR#

THERMTRIP#

TEST3

H_DPRSTP#

R72

*56/04

R152

2K/F/04

H_IGNNE#

IGNNE#

H_DPSLP#

AF1

D24

+1.05V

TEST5

DPRSTP#

DPSLP#

DPWR#

H_DPRSTP#

7,21,44

H CLK

H_STPCLK#

STPCLK#

H_DPSLP#

C928

C929

H_INTR

H_DPWR#

LINT0

LINT1

H_PWRGD

A22

A21

B22

B23

C21

H_NMI

CLK_CPU_BCLK

CPU_BSEL0

H_PWRGD

BCLK[0]

BCLK[1]

BSEL[0]

BSEL[1]

BSEL[2]

PWRGOOD

SLP#

H_SMI#

CLK_CPU_BCLK#

CPU_BSEL1

H_CPUSLP#

SMI#

*100P/50V/04

AE6

CPU_BSEL2

PSI#

PM_PSI#

*100P/50V/04

D22

SI-2 modified

resevved for power

noise

RSVD[01]

RSVD[02]

RSVD[03]

RSVD[04]

RSVD[05]

RSVD[06]

RSVD[07]

RSVD[08]

SI-2 modified --remove R72

Merom Ball-out Rev 1a

C930

C931

R157

*1K/F/04

Reserved for EMI.

C932

CPU_TEST1

CPU_TEST2

*PAD

CPU_TEST3

CPU_TEST5

T49

C933

R158

*1K/F/04

*PAD

T154

+1.05V

SI-2 modified

resevved for power

noise

C934

*100P/50V/0 4

+1.05V

C935

*100P/50V/04

For the purpose of testability, route these signals

through a ground referenced Z0 = 55ohm trace that

ends in a via that is near a GND via and is

accessible through an oscilloscope connection.

RSVD[09]

C936

*100P/50V/04

C132

*0.1U/10V/04

RSVD[10]

*100P/50V/04

CPU_TEST4

*100P/50V/04

C911

*.1U/10V/04

C730

*.1U/10V/04

*100P/50V/04

R140

*0/04

*100P/50V/04

Merom Ball-out Rev 1a

CPU_TEST6

Place C close to the

CPU_TEST4 pin. Make sure

CPU_TEST4 routing is

reference to GND and away

from other noisy signal.

VIN

+1.5V

SI-1 modified add ITP connector

Populate ITP700Flex for bringup

+1.05V

COMP0

COMP1

R22

27/F/04

ITP_TCK

COMP2

COMP3

ITP_TRST#

R21

649/F/04

ITP debug signals

R13

*51/F/04

R20

51/04

R18

39/F/04

R15

150/04

FSB

BCLK

BSEL2 BSEL1 BSEL0

+1.05V

R16

54.9/F/04

R17

27.4/F/04

R585

54.9/F/04

R584

27.4/F/04

533

133

JITP1

C904

*0.1U/10V/04

667

166

200

ITP_TDI

ITP_TMS

TDI

TMS

TCK

TDO

TRST#

VTT0

VTT1

VTAP

C905

*0.1U/10V/04

800

ITP_TCK

Comp0,2 connect with Zo=27.4ohm,Comp1,3

connect with Zo=55ohm, make those traces

length shorter than 0.5".Trace should be

at least 25 mils away from any other

toggling signal.

ITP_TDO

R19

0/04

ITP_TRST#

R14

22.6/F/04

H_RESET#

ITP_DBRESET#

ITP disable guidelines

Signal

RESET#

DBR#

DBA#

Layout Note:

Place R8

close ITP.

Resistor Value Connect To Resistor Placement

Within 2.0" of the ITP

ITP_TCK

FBO

BCLKN

BCLKP

TDI

TMS

TRST#

TCK

TDO

150 ohm +/- 5%

39 ohm +/- 1%

500-680ohm +/- 5%

27 ohm +/- 1%

VTT

CLK_CPU_ITP#

C925

ITP_BPM#0

Within 2.0" of the ITP

CLK_CPU_ITP

BPM0#

BPM1#

BPM2#

BPM3#

BPM4#

BPM5#

ITP_BPM#1

ITP_BPM#2

ITP_BPM#4

GND

Within 2.0" of the ITP

*100P/50V/04

Layout Note:

Place

R4,R361,R346

& R7 close

to CPU.

ITP_BPM#3

GND0

GND1

GND2

GND3

GND4

GND5

Within 2.0" of the ITP

PROJECT : AT3

ITP_BPM#5

150 ohm +/- 5%

VTT

Quanta Computer Inc.

NC0

NC1

GND_0

GND_1

Size

Document Number

Rev

Note: Populate R5, R8, C372 & R430 when ITP connector is populated.

Custom

*ITP700Flex

CLOCK GENERATOR

NB5/RD1/HW2

Date:

Thursday, January 11, 2007

Sheet

ICCODE:

for Merom processors

recommended design

target is 44A

VCC_CORE

U31C

U31D

A10

A12

A13

A15

A17

A18

A20

B10

B12

B14

B15

B17

B18

B20

C10

C12

C13

C15

C17

C18

D10

D12

D14

D15

D17

D18

E10

E12

E13

E15

E17

E18

E20

F10

F12

F14

F15

F17

F18

F20

AA7

AA9

AA10

AA12

AA13

AA15

AA17

AA18

AA20

AB9

AC10

AB10

AB12

AB14

AB15

AB17

AB18

AB20

AB7

AC7

AC9

AC12

AC13

AC15

AC17

AC18

AD7

AD9

AD10

AD12

AD14

AD15

AD17

AD18

AE9

AE10

AE12

AE13

AE15

AE17

AE18

AE20

AF9

AF10

AF12

AF14

AF15

AF17

AF18

AF20

VCC[001]

VCC[002]

VCC[003]

VCC[004]

VCC[005]

VCC[006]

VCC[007]

VCC[008]

VCC[009]

VCC[010]

VCC[011]

VCC[012]

VCC[013]

VCC[014]

VCC[015]

VCC[016]

VCC[017]

VCC[018]

VCC[019]

VCC[020]

VCC[021]

VCC[022]

VCC[023]

VCC[024]

VCC[025]

VCC[026]

VCC[027]

VCC[028]

VCC[029]

VCC[030]

VCC[031]

VCC[032]

VCC[033]

VCC[034]

VCC[035]

VCC[036]

VCC[037]

VCC[038]

VCC[039]

VCC[040]

VCC[041]

VCC[042]

VCC[043]

VCC[044]

VCC[045]

VCC[046]

VCC[047]

VCC[048]

VCC[049]

VCC[050]

VCC[051]

VCC[052]

VCC[053]

VCC[054]

VCC[055]

VCC[056]

VCC[057]

VCC[058]

VCC[059]

VCC[060]

VCC[061]

VCC[062]

VCC[063]

VCC[064]

VCC[065]

VCC[066]

VCC[067]

VCC[068]

VCC[069]

VCC[070]

VCC[071]

VCC[072]

VCC[073]

VCC[074]

VCC[075]

VCC[076]

VCC[077]

VCC[078]

VCC[079]

VCC[080]

VCC[081]

VCC[082]

VCC[083]

VCC[084]

VCC[085]

VCC[086]

VCC[087]

VCC[088]

VCC[089]

VCC[090]

VCC[091]

VCC[092]

VCC[093]

VCC[094]

VCC[095]

VCC[096]

VCC[097]

VCC[098]

VCC[099]

VCC[100]

VSS[001]

VSS[082]

A11

A14

A16

A19

A23

AF2

B11

B13

B16

B19

B21

B24

C11

C14

C16

C19

C22

C25

D11

D13

D16

D19

D23

D26

E11

E14

E16

E19

E21

E24

F11

F13

F16

F19

F22

F25

G23

G26

H21

H24

J22

J25

K23

K26

L21

L24

M22

M25

N23

N26

P21

P24

R22

R25

T23

T26

U21

U24

V22

V25

W23

W26

Y21

Y24

AA2

AA5

AA8

AA11

AA14

AA16

AA19

AA22

AA25

AB1

AB4

AB8

AB11

AB13

AB16

AB19

AB23

AB26

AC3

AC6

AC8

AC11

AC14

AC16

AC19

AC21

AC24

AD2

AD5

AD8

AD11

AD13

AD16

AD19

AD22

AD25

AE1

AE4

VSS[002]

VSS[003]

VSS[004]

VSS[005]

VSS[006]

VSS[007]

VSS[008]

VSS[009]

VSS[010]

VSS[011]

VSS[012]

VSS[013]

VSS[014]

VSS[015]

VSS[016]

VSS[017]

VSS[018]

VSS[019]

VSS[020]

VSS[021]

VSS[022]

VSS[023]

VSS[024]

VSS[025]

VSS[026]

VSS[027]

VSS[028]

VSS[029]

VSS[030]

VSS[031]

VSS[032]

VSS[033]

VSS[034]

VSS[035]

VSS[036]

VSS[037]

VSS[038]

VSS[039]

VSS[040]

VSS[041]

VSS[042]

VSS[043]

VSS[044]

VSS[045]

VSS[046]

VSS[047]

VSS[048]

VSS[049]

VSS[050]

VSS[051]

VSS[052]

VSS[053]

VSS[054]

VSS[055]

VSS[056]

VSS[057]

VSS[058]

VSS[059]

VSS[060]

VSS[061]

VSS[062]

VSS[063]

VSS[064]

VSS[065]

VSS[066]

VSS[067]

VSS[068]

VSS[069]

VSS[070]

VSS[071]

VSS[072]

VSS[073]

VSS[074]

VSS[075]

VSS[076]

VSS[077]

VSS[078]

VSS[079]

VSS[080]

VSS[081]

VSS[083]

VSS[084]

VSS[085]

VSS[086]

VSS[087]

VSS[088]

VSS[089]

VSS[090]

VSS[091]

VSS[092]

VSS[093]

VSS[094]

VSS[095]

VSS[096]

VSS[097]

VSS[098]

VSS[099]

VSS[100]

VSS[101]

VSS[102]

VSS[103]

VSS[104]

VSS[105]

VSS[107]

VSS[108]

VSS[109]

VSS[110]

VSS[111]

VSS[112]

VSS[113]

VSS[114]

VSS[115]

VSS[116]

VSS[117]

VSS[118]

VSS[119]

VSS[120]

VSS[121]

VSS[122]

VSS[123]

VSS[124]

VSS[125]

VSS[126]

VSS[127]

VSS[128]

VSS[129]

VSS[130]

VSS[131]

VSS[132]

VSS[133]

VSS[134]

VSS[135]

VSS[136]

VSS[137]

VSS[138]

VSS[139]

VSS[140]

VSS[141]

VSS[142]

VSS[143]

VSS[144]

VSS[145]

VSS[146]

VCC_CORE

C88

22U/10V/08

C672

10U/4V/08

C676

10U/4V/08

C683

10U/4V/08

C688

10U/4V/08

VCC_CORE

C96

22U/10V/08

C81

22U/10V/08

C693

10U/4V/08

C697

10U/4V/08

C87

22U/10V/08

8 inside cavity, north side, secondary layer.

VSS[106]

VCC_CORE

ICCP:

1before vccore stable

peak current is 4.5A

2.after vccore stable

continue current is

2.5A

C52

22U/10V/08

C42

22U/10V/08

C72

22U/10V/08

C66

22U/10V/08

C57

22U/10V/08

+1.05V

G21

VCCP[01]

VCCP[02]

J21

K21

M21

N21

R21

T21

V21

W21

VCCP[03]

VCCP[04]

VCCP[05]

VCCP[06]

VCCP[07]

VCCP[08]

VCCP[09]

VCCP[10]

VCCP[11]

VCCP[12]

VCCP[13]

VCCP[14]

VCCP[15]

VCCP[16]

VCC_CORE

+ C26

*330U/2.5V

C71

22U/10V/08

C63

22U/10V/08

C36

22U/10V/08

C95

22U/10V/08

C80

22U/10V/08

+1.5V

8 inside cavity, south side, secondary layer.

ICCA 130mA

VCC_CORE

B26

VCCA[01]

C26

VCCA[02]

C729

.01U/25V/04

C733

10U/4V/08

AD6

AF5

AE5

AF4

AE3

AF3

AE2

VID[0]

VID[1]

VID[2]

VID[3]

VID[4]

VID[5]

VID[6]

CPU_VID0

CPU_VID1

C40

22U/10V/08

C39

22U/10V/08

C35

22U/10V/08

C41

22U/10V/08

C50

22U/10V/08

C55

22U/10V/08

CPU_VID2

CPU_VID3

CPU_VID4

CPU_VID5

CPU_VID6

6 inside cavity, north side, primary layer.

Layout Note:

Place C105 near PIN

B26.

AF7

TP_VCCSENSE

VCCSENSE

TP_VCCSENSE

VCC_CORE

AE8

VSS[147]

TP_VSSSENSE

AE7

AE11

TP_VSSSENSE 44

VSSSENSE

VSS[148]

AE14

AE16

VSS[149]

VSS[150]

Merom Ball-out Rev 1a

C671

22U/10V/08

C675

10U/4V/08

C682

22U/10V/08

C687

10U/4V/08

C692

10U/4V/08

C696

10U/4V/08

AE19

VSS[151]

AE23

VSS[152]

AE26

VSS[153]

VSS[154]

AF6

VSS[155]

6 inside cavity, south side, primary layer.

AF8

VSS[156]

AF11

VSS[157]

AF13

VSS[158]

AF16

VSS[159]

AF19

VSS[160]

AF21

VSS[161]

A25

VSS[162]

AF25

VSS[163]

+1.05V

Merom Ball-out Rev 1a

C65

.1U/10V/04

C64

.1U/10V/04

C54

.1U/10V/04

C56

.1U/10V/04

C48

.1U/10V/04

C51

.1U/10V/04

Layout out:

Place these inside socket cavity on North side secondary.

PROJECT : AT3

Quanta Computer Inc.

Size

Document Number

Rev

Custom

Merom Processor (POWER)

NB5/RD1/HW2

Date:

Thursday, January 11, 2007

Sheet

+3V

R165

200/F/06

25mils

LM86VCC

C169

.1U/10V/04

R162

*0/06

SYS_SHDN#

16,42

R164

10K/04

R163

10K/04

R161

10K/04

+3V

10/20mils

LM86__SMC

SCLK

SDA

ALERT#

OVERT#

VCC

DXP

DXN

GND

H_THERMDA

LM86_SMD

C126

2200P/50V/06

R176

1M/F/06

THERM_ALERT#

H_THERMDC

THERM_ALERT#

H_THERMDC

R368

*0/06

2N7002E

close to ICH

MAX6657/GMT-781

C235

0.1U/16V/06

ADDRESS: 98H

SYS_SHDN-1#

2N7002E

add hardware protect

+3V

2N7002E

LM86_SMD

17,36,37,41,48

MBDATA

+3V

2N7002E

LM86__SMC

17,36,37,41,48

MBCLK

PROJECT : AT3

Quanta Computer Inc.

Size

Document Number

Rev

THERMAL LM86

NB5/RD1/HW2

Date:

Thursday, January 11, 2007

Sheet

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