AT8-1229.pdf

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PCB STACK UP
Altlantis/Apollo
Block Diagram
RUN POWER
SW
AC/BATT
CONNECTOR
CPU VR
LAYER 1 : TOP
PG 34
LAYER 2 : SGND1
Turion64
PG 38
PG 36,37
BATT
CHARGER
Sempron
LAYER 3 : IN1
PG 34
DC/DC
+3VSUS
+5VSUS
A
A
LAYER 4 : IN2
DDRII-SODIMM1
DDRII 667mhz
LAYER 5 : VCC
PG 5
25W/35W
LAYER 6 : IN3
AMD Socket S1 638P
PG 33
DDRII-SODIMM2
DDRII 667mhz
LAYER 7 : SGND2
PG 2,3,4
PG 5
LAYER 8 : BOT
HT Link
Option for 17" only
NVDIA G3-64 for 15.4"
PCI-E
PCI-Express 16X
nVIDIA
NVDIA G3-128 for 17"
HDMI CON
PG 18
C51M/D
Graphics
Integraded VGA Function
PG 9,10,11,12,13,14
TV_OUT
Mini PCI-E Card
Express Card
Cable
Docking
VGA
PCI Express Mini Card
(NEW CARD)
TV_OUT
RJ-45
CIR/Pwr btn
SPDIF Out
Stereo MIC
Headphone J ack
(Wireless LAN/WAN)
PG 28
CRT/S-VIDEO
B
B
PG 27
468PIN
CRT_OUT
PG 19
LVDS(2 Channel)
Panel Connector
SIM CARD
PG 6,7,8
15" / 17"
PG 27
PG 18
USB Port
VOL Cntr
HT Link
PG 31
CLOCK
INTERFACE
USB2.0
Option for 17" only
SATA2
Bluetooth
USB2.0 I/O Ports
PG 26
Camera
Mini PCI-E Card x1
Express Card x1
Cable Docking x1
SATA - HDD
nVIDIA
X3
1.3MP
PG 28
PG 23
PG 28
MCP51M
508PIN
PCI BUS / 33MHz
SATA0
SATA - HDD
LAN
PG 26
C
C
Azalia
PATA
(66/100/133)
PG 15,16,17
PATA-
CD-ROM
REALTEK
RICOH
Two-element
microphone
PG 26
RTL8201CL
(10/100)/
REL8211B
(10/100 /Gigabit)
RICOH 832
Conexant
PG 23
Venice AMOM
LPC
PG 21
CX20549-12
Audio Jacks
PG 20
PG 23
(Phone/SPDIF/
MIC)
Keyboard
PG 23
Touch Pad
PG 29
ENE KBC
IEEE1394
CONN
Memory
CardReader
RJ45
VAULE DEFINE
KB3920 Bx
A=0603,B=0805,C=1206,F=1%,
OTHER IS 0402
CIR
AUDIO
Amplifier
MDC DAA
PG 23
PG 21
PG 22
PG 20
PG 25
PG 24
Capacitive Sense
SW
EXAMPLE
PG 30
PG 29
PCI ROUTING
TABLE
10R=10ohm(0402)
10A=10ohm(0603)
10B=10ohm(0805)
10C=10ohm(1206)
10/F=10ohm(0402 and 1%)
IDSEL
AD21
INTERUPT
INTA#,INTB#
DEVICE
Jack to
Speaker
MODEM RJ 11
REQ0# / GNT0#
RICOH832
D
D
PG 25
PG 20
PROJECT : AT8
FAN
Flash
Quanta Computer Inc.
PG 31
PG 30
Size
Document Number
Rev
Custom
Block Diagram
1A
NB5/RD2/HW1
Date:
Thursday, December 29, 2005
Sheet
1
of
38
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02
HT_RXD#[15..0]
HT_TXD[15..0]
W/S= 15 mil/20mil
6
HT_RXD#[15..0]
6
HT_TXD[15..0]
HT_RXD[15..0]
HT_TXD#[15..0]
CPU2.5V
L80
FBMJ3216HS800 - T
6
HT_RXD[15..0]
6
HT_TXD#[15..0]
2.5V
C711
U26A
C43
.22U
C703
.22U
1.2V_HT
1.2V_HT
C707
4.7UA
D1
AE2
V_HT0_A1
V_HT0_B1
C706
4.7UA
1.2V_HT
1.2V_HT
1.2V_HT
D2
AE3
1.2V_HT
C705
180P/50V
100U/6032
V_HT0_A2
V_HT0_B2
U26E
C702
4.7UA
1.2V_HT
C709
180P/50V
D3
AE4
V_HT0_A3
V_HT0_B3
C704
.22U
1.2V_HT
CPUTEST2
CPU2.5V
CPU2.5V
C712
4.7UA
D4
AE5
AB6
F9
1.2V_HT
T14
V_HT0_A4
V_HT0_B4
TEST2
VDDA_1
CPUTEST3
CPU2.5V
CPU2.5V
Y6
F8
C52
3300P/X7R
T158
TEST3
VDDA_2
HT_RXD0
HT_RXD1
HT_RXD2
HT_RXD3
HT_TXD0
HT_TXD2
CPU_THERMDA
E3
AD1
W8
HT_RXD0
HT_TXD0
THERMDA
E1
AC2
HT_TXD1
CPU_THERMDC
W7
B7
HTCPU_RST1#
R457
*300R
1.8VSUS
HT_RXD1
HT_TXD1
THERMDC
RESET#
CPUTEST6
HTCPU_PWROK1
G3
AB1
AA6
A7
R460
*300R
HT_RXD2
HT_TXD2
T2
TEST6
PWROK
1.8VSUS
HT_TXD3
CPUTEST7
HTCPU_STOP1#
R450
*300R
G1
AA2
C3
F10
T164
1.8VSUS
A
HT_RXD3
HT_TXD3
TEST7
LDTSTOP#
A
HT_RXD4
HT_RXD6
J1
W2
HT_TXD4
CPUTEST8
C4
HT_RXD4
HT_TXD4
T1
TEST8
HT_RXD5
HT_RXD7
HT_TXD5
L3
V1
C2
HT_RXD5
HT_TXD5
TEST9
HT_TXD6
CPUTEST10
CPUHTREF0
R437
44.2F
L1
U2
K8
R6
T159
HT_RXD6
HT_TXD6
TEST10
HTREF0
HT_TXD7
CPUTEST12
CPUHTREF1
N3
T1
AC8
P6
R436
44.2F
T12
HT_RXD7
HT_TXD7
TEST12
HTREF1
1.2V_HT
HT_RXD8
HT_TXD8
CPU_CORE_FB
E5
AD4
AA7
F6
HT_RXD8
HT_TXD8
TEST13
VDD_FB
CPU_CORE_FB38
CPU_CORE_FB#38
HT_RXD9
F3
AD5
HT_TXD9
CPUTEST14
C7
E6
CPU_CORE_FB#
HT_RXD9
HT_TXD9
T9
TEST14
VDD_FB#
HT_RXD10
HT_TXD10
CPUTEST15
CPU_SUS_FB
G5
AB4
F7
W9
T5
HT_RXD10
HT_TXD10
TEST15
VDDIO_FB
CPU_SUS_FB37
HT_RXD11
HT_TXD11
CPUTEST16
H3
AB5
E7
Y9
T3
HT_RXD11
HT_TXD11
TEST16
VDDIO_FB#
HT_RXD12
HT_TXD12
CPUTEST17
CPUCLKIN
CPUCLKIN#
K3
Y5
TEST PU/PL MUST
FOLLOW ERRATUM
133
REVISION GUIDE
FROM AMD NPT
0Fh CPU
D7
A9
HT_RXD12
HT_TXD12
T 7
TEST17
CLKIN
T173
T39
HT_RXD13
HT_TXD13
R58
300R
CPUTEST18
L5
V4
H10
A8
HT_RXD13
HT_TXD13
TEST18
CLKIN#
T170
HT_RXD14
M3
V5
HT_TXD14
R53
300R
CPUTEST19
G9
G10
CPU_DBRDY
HT_RXD14
HT_TXD14
TEST19
DBRDY
HT_RXD15
HT_TXD15
CPUTEST20
CPU_DBRDY#
N5
T4
AF7
E10
T 1 62
HT_RXD15
HT_TXD15
TEST20
DBREQ#
T31
R48
300R
CPUTEST21
CPU_TMS
CPU_TCK
AB8
AA9
T18
TEST21
TMS
HT_RXD#0
HT_RXD#1
HT_RXD#2
HT_RXD#3
HT_RXD#4
HT_RXD#5
HT_RXD#6
HT_RXD#7
HT_RXD#8
HT_RXD#9
HT_RXD#10
HT_RXD#11
HT_RXD#12
HT_RXD#13
HT_RXD#14
HT_RXD#15
E2
AC1
HT_TXD#0
HT_TXD#1
HT_TXD#2
HT_TXD#3
HT_TXD#4
HT_TXD#5
HT_TXD#6
HT_TXD#7
HT_TXD#8
HT_TXD#9
HT_TXD#10
HT_TXD#11
HT_TXD#12
HT_TXD#13
HT_TXD#14
HT_TXD#15
CPUTEST22
AE8
AC9
HT_RXD#0
HT_TXD#0
T165
TEST22
TCK
T167
CPUTEST23
CPU_TRST#
F1
AC3
AD7
AD9
T160
HT_RXD#1
HT_TXD#1
TEST23
TRST#
T174
G2
AA1
CPUTEST24
AE7
AF9
CPU_TDI
HT_RXD#2
HT_TXD#2
T 1 61
TEST24
TDI
T176
R55
510F
CPUTEST25
CPU_TDO
H1
AA3
E9
AE9
HT_RXD#3
HT_TXD#3
1.8VSUS
1.8VSUS
TEST25
TDO
T17 5
R49
510F
CPUTEST25#
CPU_PRES#
R425
1K
K1
W3
E8
AC6
1.8VSUS
HT_RXD#4
HT_TXD#4
TEST25#
CPU_PRESENT#
L2
U1
R429
300R
CPUTEST26
AE6
A3
HT_RXD#5
HT_TXD#5
TEST26
PSI#
C PU_PSI#38
CPUTEST27
CPU_VID0_L
M1
U3
AF8
B5
T169
HT_RXD#6
HT_TXD#6
TEST27
VID0
1.8VSUS
N2
R1
CPUTEST28
J7
C5
CPU_VID1_L
CPU_VID2_L
CPU_VID3_L
CPU_VID5_L
R33
*300R
HT_RXD#7
HT_TXD#7
T4
TEST28
VID1
CPUTEST28#
R30
300R
F5
AD3
H8
A4
HT_RXD#8
HT_TXD#8
T6
TEST28#
VID2
FBCLKOUT
R21
*300R
F4
AC5
C9
A6
HT_RXD#9
HT_TXD#9
TEST29
VID3
H5
AB3
R52
80.6F
FBCLKOUT#
C8
C6
CPU_VID4_L
R37
*300R
HT_RXD#10
HT_TXD#10
TEST29#
VID4
R31
*300R
H4
AA5
A5
HT_RXD#11
HT_TXD#11
VID5
K4
W5
ROUTE TRACES 80OHM DIFF
IMPEDENCE 8/5/20 SPACING
AF5
CPU_SID
CPU_SIC
R23
*300R
HT_RXD#12
HT_TXD#12
SID
M5
V3
AF4
HT_RXD#13
HT_TXD#13
SIC
CPU_PROCHOT#
M4
U5
AC7
1.8VSUS
1.8VSUS
HT_RXD#14
HT_TXD#14
PROCHOT#
P5
T3
AF6
CPU_THERMIP#
R426
300R
HT_RXD#15
HT_TXD#15
THERMTRIP#
R433
300R
B
B3
B
RSVD_1
HT_CPU_UPCLK0
HT_CPU_UPCLK1
HT_CPU_UPCLK#0
HT_CPU_UPCLK#1
HT_CPU_UPCTL0
HT_CPU_DWNCLK0
HT_CPU_DWNCLK1
HT_CPU_DWNCLK#0
HT_CPU_DWNCLK#1
HT_CPU_DWNCTL0
HT_CPU_DWNCTL1
J3
Y1
H19
R22
6
HT_CPU_UPCLK0
HT_CPU_DWNCLK06
HT_CPU_DWNCLK16
HT_CPU_DWNCLK#06
HT_CPU_DWNCLK#16
HT_CPU_DWNCTL06
HT_RXCLK0
HT_TXCLK0
RSVD_2
RSVD_12
J5
Y4
1.8VSUS
H18
H16
6
HT_CPU_UPCLK#0
HT_CPU_UPCLK1
HT_RXCLK1
HT_TXCLK1
RSVD_3
RSVD_13
CPUCLKIN
CPUCLKIN#
C7163900P
W18
R23
RSVD_4
RSVD_14
CPU_CLK6
CPU_CLK#6
J2
W1
CPU_SID
CPU_SIC
R428
*300R
D5
R25
6
HT_RXCLK#0
HT_TXCLK#0
RSVD_5
RSVD_15
R427
*300R
C7143900P
K5
Y3
N20
B18
6
HT_CPU_UPCLK#1
HT_RXCLK#1
HT_TXCLK#1
RSVD_6
RSVD_16
R422
300R
P20
R24
RSVD_7
RSVD_17
CPUCLKIN#
CPUCLKIN
N1
R2
P19
C1
R446
169F
6
HT_CPU_UPCTL0
HT_RXCTL0
HT_TXCTL0
RSVD_8
RSVD_18
HT_CPU_UPCTL1
P3
T5
N19
H6
1.2V_HT
HT_RXCTL1
HT_TXCTL1
RSVD_9
RSVD_19
R435
49.9F
T157
P22
G6
KEEP TRACE RESISTOR <0.6" FROM CPU
AND TRACE TO AC CAP <1.25"
CPUVID1 PU REQUIRED
FOR COMPATIBILITY WITH
FUTURE CPU
RSVD_10
RSVD_20
P1
R3
If AMD SI is not used
SID can be left, SIC
300ohm to VSS.
R26
AA8
6
HT_CPU_UPCTL#0
HT_RXCTL#0
HT_TXCTL#0
HT_CPU_DWNCTL#06
RSVD_11
RSVD_21
HT_CPU_UPCTL#1
HT_CPU_DWNCTL#1
P4
R5
HT_RXCTL#1
HT_TXCTL#1
R434
49.9F
T156
AMD S1 SOCKET
AMD S1 SOCKET
HT_RXCTL1/HT_RXCRL#1 MUST <1.5" FROM CPU PIN
MUST KEEP LOW DURING S3-S5 TO MEET HT IO LINK SPEC
CPU THERMAL SENSOR & CONTROL
HT LINK CONTROL LEVEL SHIFTER
OVER TEMP CONTROL
Q35
PDTC144EU
R62
200R
6648VCC
C88
.1U
3V
1.8VSUS
CPU_THERMIP#
1
3
MCP_THERMIP#17
U1
U25
10/20mils
2
1
6
HTCPU_RST#
R64
2.7K
LM86_SMC
LM86_SMD
HTCPU_RST1#
PLACE CLOSE CPU
8
1
4
3V
SCLK
VCC
CPU_THERMDA
THERM_ALERT#
17,30
ECPWROK
R63
2.7K
D31
CH500H
7
2
SDA
DXP
C120
2200P/X7R
74LVC1G08GW
3V
C
C
THERM_ALER T#
6
3
R423
4.7K
ALERT#
DXN
1.8VSUS
1.8VSUS
4
5
CPU_THERMDC
17
THERM_OVER#
OVERT#
GND
U28
CPU OT THERM IC THERMTRIP TO SHUTDOWN SYS FROM SB
R72
*10K
2
1
6
HTCPU_PWRGD
3V
HTCPU_PWROK1
MAX6657
4
R73
10K
G781P8
ECPWROK
3V
ADDRESS: 98H
THERM_OVER#
1
3
CPU_PROCHOT#
74LVC1G08GW
Q36
PDTC144EU
3
1
LM86_SMC
30,34
MBCLK
LM86_SMC5
1.8VSUS
30
EC_PROCHOT#
Q8
RHU002N06
D29
CH500H
U24
2
1
5
DIMM_THEM#
6
HTCPU_STOP#
LM86_SMD
HTCPU_STOP1#
D30
*CH500H
1
3
4
5
LM86_SMD
MBDATA30,34
ECPWROK
3V
3V
Q9
RHU002N06
74LVC1G08GW
CPU PROCHOT INPUT FROM THERMAL IC OR SODIMM SENSOR
MBCLK/MBDATA NEED PU TO 3VPCU
FOLLOW AMD AND NVIDIA RECOMMEND
3V
NEED TO CONFIRM NVIDIA FOR THE USAGE CONNECTION TO SB
R19
0A
R43
0A
R40
0R
R442
*8.2K
2.5V
CPU_VID1_L
CPU_VID3_L
CPU_VID4_L
CPU_FETGATE
3
1
3
1
3
1
R441
*34.8KF
CPU_VID117,38
CPU_VID317,38
CPU_VID417,38
Q4
*RHU002N06
Q7
*RHU002N06
Q5
*RHU002N06
D
D
3V
3V
3V
R20
*4.7K
R34
*4.7K
R32
*4.7K
CPU_FETGATE
CPU_FETGATE
CPU_FETGATE
PROJECT : AT8
R36
*4.7K
R22
*4.7K
R35
*4.7K
3V
3V
3V
Q6
*RHU002N06
3
Q2
*RHU002N06
3
Q3
*RHU002N06
3
Quanta Computer Inc.
CPU_VID0_L
1
CPU_VID2_L
1
CPU_VID5_L
1
CPU_VID017,38
CPU_VID217,38
CPU_VID517,38
Size
Document Number
Rev
Custom
CPU(HT_LINK /CTL)
1A
R38
0R
R18
0A
R39
0A
NB5/RD2/HW1
Date:
Thursday, December 29, 2005
Sheet
2
of
38
1
2
3
4
5
6
7
8
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
 
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03
U26B
U26C
M_A_DQ63
M_A_DQM7
M_B_DQ63
M_B_DQ62
M_B_DQ61
M_B_DQ60
M_B_DQ59
M_B_DQ58
M_B_DQ57
M_B_DQ56
M_B_DQ55
M_B_DQ54
M_B_DQ53
M_B_DQ52
M_B_DQ51
M_B_DQ50
M_B_DQ49
M_B_DQ48
M_B_DQ47
M_B_DQ46
M_B_DQ45
M_B_DQ44
M_B_DQ43
M_B_DQ42
M_B_DQ41
M_B_DQ40
M_B_DQ39
M_B_DQ38
M_B_DQ37
M_B_DQ36
M_B_DQ35
M_B_DQ34
M_B_DQ33
M_B_DQ32
M_B_DQ31
M_B_DQ30
M_B_DQ29
M_B_DQ28
M_B_DQ27
M_B_DQ26
M_B_DQ25
M_B_DQ24
M_B_DQ23
M_B_DQ22
M_B_DQ21
M_B_DQ20
M_B_DQ19
M_B_DQ18
M_B_DQ17
M_B_DQ16
M_B_DQ15
M_B_DQ14
M_B_DQ13
M_B_DQ12
M_B_DQ11
M_B_DQ10
M_B_DQ9
M_B_DQ8
M_B_DQ7
M_B_DQ6
M_B_DQ5
M_B_DQ4
M_B_DQ3
M_B_DQ2
M_B_DQ1
M_B_DQ0
M_B_DQM7
M_B_DQM6
M_B_DQM5
M_B_DQM4
M_B_DQM3
M_B_DQM2
M_B_DQM1
M_B_DQM0
AA12
Y13
AD11
AD12
MA_DATA[63]
MA_DM[7]
MB_DATA[63]
MB_DM[7]
M_A_DQ62
M_A_DQM6
AB12
AB16
AF11
AC16
MA_DATA[62]
MA_DM[6]
MB_DATA[62]
MB_DM[6]
M_A_DQ61
M_A_DQM5
AA14
Y19
AF14
AE22
MA_DATA[61]
MA_DM[5]
MB_DATA[61]
MB_DM[5]
M_A_DQ60
AB14
AC24
M_A_DQM4
AE14
AB26
MA_DATA[60]
MA_DM[4]
MB_DATA[60]
MB_DM[4]
M_A_DQ59
M_A_DQM3
W11
F24
Y11
E25
MA_DATA[59]
MA_DM[3]
MB_DATA[59]
MB_DM[3]
M_A_DQ58
M_A_DQM2
Y12
E19
AB11
A22
MA_DATA[58]
MA_DM[2]
MB_DATA[58]
MB_DM[2]
M_A_DQ57
M_A_DQM1
AD13
C15
AC12
B16
MA_DATA[57]
MA_DM[1]
MB_DATA[57]
MB_DM[1]
M_A_DQ56
M_A_DQM0
AB13
E12
AF13
A12
MA_DATA[56]
MA_DM[0]
MB_DATA[56]
MB_DM[0]
M_A_DQ55
AD15
AF15
MA_DATA[55]
MB_DATA[55]
M_A_DQ54
AB15
AF16
MA_DATA[54]
MB_DATA[54]
M_A_DQ53
AB17
AC18
A
MA_DATA[53]
MB_DATA[53]
A
M_A_DQ52
Y17
W12
M_A_DQS7
AF19
AF12
M_B_DQS7
MA_DATA[52]
MA_DQS[7]
MB_DATA[52]
MB_DQS[7]
M_A_DQ51
M_A_DQS6
M_B_DQS6
Y14
Y15
AD14
AE16
MA_DATA[51]
MA_DQS[6]
MB_DATA[51]
MB_DQS[6]
M_A_DQ50
M_A_DQS5
M_B_DQS5
W14
AB19
AC14
AF21
MA_DATA[50]
MA_DQS[5]
MB_DATA[50]
MB_DQS[5]
M_A_DQ49
M_A_DQS4
M_B_DQS4
W16
AD23
AE18
AC25
MA_DATA[49]
MA_DQS[4]
MB_DATA[49]
MB_DQS[4]
M_A_DQ48
M_A_DQS3
M_B_DQS3
AD17
G22
AD18
F26
MA_DATA[48]
MA_DQS[3]
MB_DATA[48]
MB_DQS[3]
M_A_DQ47
Y18
C22
M_A_DQS2
AD20
A24
M_B_DQS2
MA_DATA[47]
MA_DQS[2]
MB_DATA[47]
MB_DQS[2]
M_A_DQ46
M_A_DQS1
M_B_DQS1
AD19
G16
AC20
D16
MA_DATA[46]
MA_DQS[1]
MB_DATA[46]
MB_DQS[1]
M_A_DQ45
M_A_DQS0
M_A_DQS#7
M_B_DQS0
AD21
G13
AF23
C12
MA_DATA[45]
MA_DQS[0]
MB_DATA[45]
MB_DQS[0]
M_A_DQ44
M_B_DQS#7
AB21
W13
AF24
AE12
MA_DATA[44]
MA_DQS#[7]
MB_DATA[44]
MB_DQS#[7]
M_A_DQ43
M_A_DQS#6
M_B_DQS#6
AB18
W15
AF20
AD16
MA_DATA[43]
MA_DQS#[6]
MB_DATA[43]
MB_DQS#[6]
M_A_DQ42
AA18
AB20
M_A_DQS#5
AE20
AF22
M_B_DQS#5
MA_DATA[42]
MA_DQS#[5]
MB_DATA[42]
MB_DQS#[5]
M_A_DQ41
M_A_DQS#4
M_A_DQS#2
M_B_DQS#4
AA20
AC23
AD22
AC26
MA_DATA[41]
MA_DQS#[4]
MB_DATA[41]
MB_DQS#[4]
M_A_DQ40
M_A_DQS#3
Tolerance is
+-10%
M_B_DQS#3
Y20
G21
AC22
E26
MA_DATA[40]
MA_DQS#[3]
MB_DATA[40]
MB_DQS#[3]
M_A_DQ39
AA22
C21
AE25
A23
M_B_DQS#2
MA_DATA[39]
MA_DQS#[2]
MB_DATA[39]
MB_DQS#[2]
M_A_DQ38
M_A_DQS#1
M_B_DQS#1
Y22
G15
AD26
C16
MA_DATA[38]
MA_DQS#[1]
MB_DATA[38]
MB_DQS#[1]
M_A_DQ37
W21
H13
M_A_DQS#0
AA25
B12
M_B_DQS#0
MA_DATA[37]
MA_DQS#[0]
MB_DATA[37]
MB_DQS#[0]
M_A_DQ36
W22
AA26
MA_DATA[36]
MB_DATA[36]
M_A_DQ35
AA21
AE24
MA_DATA[35]
MB_DATA[35]
M_A_DQ34
AB22
E16
M_A_CK1
C125 1 .5P
AD24
TRACE FROM CAP TO CPU MUST BE LESS
THAN 1200MILS MAX NECKDOWN TO &
FROM CAPS IS 500MILS
MA_DATA[34]
MA0_CLK[1]
M_A_CLK15
M_A_CLK1#5
MB_DATA[34]
M_A_DQ33
M_A_CK1#
AB24
F16
AA23
MA_DATA[33]
MA0_CLK#[1]
MB_DATA[33]
M_A_DQ32
Y24
AA24
MA_DATA[32]
MB_DATA[32]
M_A_DQ31
H22
G24
MA_DATA[31]
MB_DATA[31]
M_A_DQ30
H20
G23
MA_DATA[30]
MB_DATA[30]
M_A_DQ29
E22
D26
MA_DATA[29]
MB_DATA[29]
M_A_DQ28
M_A_CK2
C127 1 .5P
E21
Y16
C26
MA_DATA[28]
MA0_CLK[2]
M_A_CLK25
M_A_CLK2#5
MB_DATA[28]
M_A_DQ27
J19
AA16
M_A_CK2#
G26
MA_DATA[27]
MA0_CLK#[2]
MB_DATA[27]
M_A_DQ26
H24
G25
C140 1 .5P
MA_DATA[26]
MB_DATA[26]
M_B_CLK15
M_A_DQ25
F22
E24
M_B_CLK1#5
MA_DATA[25]
MB_DATA[25]
M_A_DQ24
F20
E23
A17
M_B_CK1
MA_DATA[24]
MB_DATA[24]
MB0_CLK[1]
M_A_DQ23
M_B_CK1#
B
C23
TRACE FROM CAP TO CPU MUST BE LESS
THAN 1200MILS MAX NECKDOWN TO &
FROM CAPS IS 500MILS
C24
A18
B
MA_DATA[23]
MB_DATA[23]
MB0_CLK#[1]
M_A_DQ22
B22
B24
MA_DATA[22]
MB_DATA[22]
M_A_DQ21
F18
C20
MA_DATA[21]
MB_DATA[21]
M_A_DQ20
C7311.5P
E18
B20
MA_DATA[20]
MB_DATA[20]
M_B_CLK25
M_A_DQ19
E20
C25
AF18
M_B_CK2
MA_DATA[19]
MB_DATA[19]
MB0_CLK[2]
M_B_CLK2#5
M_A_DQ18
M_B_CK2#
D22
D24
AF17
MA_DATA[18]
MB_DATA[18]
MB0_CLK#[2]
M_A_DQ17
C19
A21
MA_DATA[17]
MB_DATA[17]
M_A_DQ16
G18
D20
MA_DATA[16]
MB_DATA[16]
M_A_DQ15
Tolerance is
+-10%
G17
D18
MA_DATA[15]
MB_DATA[15]
M_A_DQ14
C17
C18
MA_DATA[14]
MB_DATA[14]
M_A_DQ13
M_B_BA2
M_B_BA1
F14
D14
K26
MA_DATA[13]
MB_DATA[13]
MB_BANK[2]
M_A_DQ12
E14
C14
T26
MA_DATA[12]
MB_DATA[12]
MB_BANK[1]
M_A_DQ11
H17
A20
U26
M_B_BA0
MA_DATA[11]
MB_DATA[11]
MB_BANK[0]
M_A_DQ10
M_A_BA2
M_A_BA1
E17
K22
A19
MA_DATA[10]
MA_BANK[2]
MB_DATA[10]
M_A_DQ9
E15
R20
A16
MA_DATA[9]
MA_BANK[1]
MB_DATA[9]
M_A_DQ8
M_A_BA0
H15
T22
A15
MA_DATA[8]
MA_BANK[0]
MB_DATA[8]
M_A_DQ7
M_B_RAS#
E13
A13
U24
MA_DATA[7]
MB_DATA[7]
MB_RAS#
M_A_DQ6
C13
D12
V26
M_B_CAS#
MA_DATA[6]
MB_DATA[6]
MB_CAS#
M_A_DQ5
M_B_WE#
H12
E11
U22
MA_DATA[5]
MB_DATA[5]
MB_WE#
M_A_DQ4
H11
G11
MA_DATA[4]
MB_DATA[4]
M_A_DQ3
M_A_RAS#
M_A_CAS#
G14
T20
B14
MA_DATA[3]
MA_RAS#
MB_DATA[3]
M_A_DQ2
H14
U20
A14
MA_DATA[2]
MA_CAS#
MB_DATA[2]
M_A_DQ1
F12
U21
M_A_WE#
A11
Y26
M_B_CS#3
M_B_CS#2
M_B_CS#0
MA_DATA[1]
MA_WE#
MB_DATA[1]
MB0_CS#[3]
M_A_DQ0
G12
C11
J24
MA_DATA[0]
MB_DATA[0]
MB0_CS#[2]
M_B_CS#1
W24
MB0_CS#[1]
U23
MB0_CS#[0]
M_A_A15
M_A_CS#3
M_B_A15
M_B_A14
M_B_A13
M_B_A12
M_B_A11
M_B_A10
M_B_A9
M_B_A8
M_B_A7
M_B_A6
M_B_A5
M_B_A4
M_B_A3
M_B_A2
M_B_A1
M_B_A0
K19
V19
J25
MA_ADD[15]
MA0_CS#[3]
MB_ADD[15]
M_A_A14
K20
J22
M_A_CS#2
J26
MA_ADD[14]
MA0_CS#[2]
MB_ADD[14]
1.8VSUS
M_A_A13
M_A_CS#1
M_B_CKE1
V24
V22
W25
H26
MA_ADD[13]
MA0_CS#[1]
MB_ADD[13]
MB_CKE[1]
M_A_A12
M_A_CS#0
M_B_CKE0
K24
T19
L23
J23
C
MA_ADD[12]
MA0_CS#[0]
MB_ADD[12]
MB_CKE[0]
C
M_A_A11
L20
L25
MA_ADD[11]
MB_ADD[11]
M_A_A10
R19
U25
MA_ADD[10]
MB_ADD[10]
M_A_A9
L19
L24
W23
M_B_ODT1
M_B_ODT0
MA_ADD[9]
MB_ADD[9]
MB0_ODT[1]
M_A_A8
M_A_CKE1
R79
2KF
L22
J20
M26
W26
MA_ADD[8]
MA_CKE[1]
MB_ADD[8]
MB0_ODT[0]
M_A_A7
M_A_CKE0
L21
J21
L26
MA_ADD[7]
MA_CKE[0]
MB_ADD[7]
M_A_A6
VTERM_FB
M19
N23
Y10
MA_ADD[6]
MB_ADD[6]
VTT_SENSE
VTERM_FB37
M_A_A5
M20
N24
MA_ADD[5]
MB_ADD[5]
M_A_A4
M24
N25
W17
C51M_VREF
MA_ADD[4]
MB_ADD[4]
M_VREF
M_A_A3
M_A_ODT1
M22
V20
N26
MA_ADD[3]
MA0_ODT[1]
MB_ADD[3]
M_A_A2
M_A_ODT0
MEMZN
MEMZP
R458
39.2F
N22
U19
P24
AE10
1.8VSUS
MA_ADD[2]
MA0_ODT[0]
MB_ADD[2]
M_ZN
M_A_A1
N21
P26
MA_ADD[1]
MB_ADD[1]
M_A_A0
R77
2KF
R21
T24
AF10
MA_ADD[0]
MB_ADD[0]
M_ZP
R461
39.2F
C151
1000P/X7R
C139
.1U
?mil
AMD S1 SOCKET
AMD S1 SOCKET
C51MVREF : W =20MIL AND SPACE = 20MIL
M_A_DQ[63..0]
M_A_A[15..0]
M_A_DQM[7..0]
M_A_DQS[7..0]
M_A_DQS#[7..0]
M_A_BA[2..0]
M_A_CS#[3..0]
M_B_DQ[63..0]
M_B_DQM[7..0]
5
M_A_DQ[63..0]
M_A_DQM[7..0]5
M_A_DQS[7..0]5
M_A_DQS#[7..0]5
M_A_BA[2..0]4,5
M_A_CS#[3..0]4,5
5
M_B_DQ[63..0]
M_B_DQM[7..0]5
M_B_DQS[7..0]5
M_B_DQS#[7..0]5
M_B_CS#[3..0]4,5
M_B_A[15..0]
M_B_DQS[7..0]
4,5
M_A_A[15..0]
4,5
M_B_A[15..0]
M_B_DQS#[7..0]
M_B_BA[2..0]
M_B_BA[2..0]4,5
M_B_CS#[3..0]
M_A_RAS#
M_A_WE#
M_A_CKE1
M_A_CKE0
M_A_ODT1
M_A_ODT0
M_B_RAS#
M_B_CAS#
M_B_WE#
M_A_RAS#4,5
M_B_RAS#4,5
M_B_WE#4,5
M_B_CKE04,5
M_B_ODT14,5
M_A_CAS#
M_A_CAS#4,5
M_B_CAS#4,5
M_A_WE#4,5
M_B_CKE1
M_B_CKE0
M_A_CKE14,5
M_B_CKE14,5
M_A_CKE04,5
M_A_ODT04,5
M_B_ODT1
D
D
M_A_ODT14,5
M_B_ODT0
M_B_ODT04,5
PROJECT : AT8
Quanta Computer Inc.
Size
Document Number
Rev
Custom
CPU(MEM/IF)
1A
NB5/RD2/HW1
Date:
Thursday, December 29, 2005
Sheet
3
of
38
1
2
3
4
5
6
7
8
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
 
1
2
3
4
5
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7
8
04
CPU POWER PLANE AND BY PASS CAP
DDR2 TERMINATION BYPASS CAP
VCC_CORE
1.8VSUS
U26D
U26F
V CC_CORE
VCC_CORE
VCC_CORE
1.8VSUS
22UB/X7R
C69
AC4
H25
C164
.01U
AA4
J6
VDD1
VDDIO1
VSS1
VSS66
22UB/X7R
C68
1.8VSUS
1.8VSUS
C149
.01U
AD2
J17
AA11
J8
VDD2
VDDIO2
VSS2
VSS67
22UB/X7R
C105
VCC_CORE
G4
K18
1.8VSUS
C205
180PA/50V
AA13
J10
VDD3
VDDIO3
VSS3
VSS68
.01U
C49
C198
180PA/50V
CHANNEL A
CHANNEL B
H2
K21
AA15
J12
VDD4
VDDIO4
VSS4
VSS69
.22U
C47
VCC_CORE
1.8VSUS
C159
.22U
J9
K23
AA17
J14
VDD5
VDDIO5
VSS5
VSS70
VCC_CORE
1.8VSUS
1.8VSUS
1.8VSUS
.22U
C48
J11
K25
C796
4.7UA
AA19
J16
VDD6
VDDIO6
VSS6
VSS71
180PA/50V
C64
VCC_CORE
C809
4.7UA
J13
L17
AB2
J18
VDD7
VDDIO7
VSS7
VSS72
32,37
SMDDR_VTERM
22UB/X7R
C71
VCC_CORE
J15
M18
C807
4.7UA
AB7
K2
VDD8
VDDIO8
VSS8
VSS73
VCC_CORE
1.8VSUS
22UB/X7R
C103
K6
M21
C795
4.7UA
AB9
K7
VDD9
VDDIO9
VSS9
VSS74
22UB/X7R
C102
VCC_CORE
1.8VSUS
C173
.22U
K10
M23
AB23
K9
A
VDD10
VDDIO10
VSS10
VSS75
A
22UB/X7R
C70
VCC_CORE
K12
M25
1.8VSUS
1.8VSUS
C170
.22U
AB25
K11
VDD11
VDDIO11
VSS11
VSS76
22UB/X7R
C44
VCC_CORE
C163
.22U
K14
N17
AC11
K13
VDD12
VDDIO12
VSS12
VSS77
22UB/X7R
C104
VCC_CORE
1.8VSUS
C130
22UB/X7R
SMDDR_VTERM
C299
.1U
SMDDR_VTERM
C414
.1U
K16
P18
AC13
K15
VDD13
VDDIO13
VSS13
VSS78
VCC_CORE
1.8VSUS
SMDDR_VTERM
SMDDR_VTERM
L4
P21
C794
22UB/X7R
AC15
K17
C381
.1U
C298
.1U
VDD14
VDDIO14
VSS14
VSS79
VCC_CORE
1.8VSUS
1.8VSUS
C138
22UB/X7R
SMDDR_VTERM
SMDDR_VTERM
C358
.1U
SMDDR_VTERM
C415
.1U
L7
P23
AC17
L6
VDD15
VDDIO15
VSS15
VSS80
VCC_CORE
L9
P25
C126
22UB/X7R
AC19
L8
SMDDR_VTERM
C359
.1U
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
C409
.1U
VDD16
VDDIO16
VSS16
VSS81
VCC_CORE
1.8VSUS
C129
22UB/X7R
C362
.1U
C303
.1U
L11
R17
AC21
L10
VDD17
VDDIO17
VSS17
VSS82
VCC_CORE
1.8VSUS
C800
22UB/X7R
SMDDR_VTERM
C379
.1U
C410
.1U
L13
T18
AD6
L12
VDD18
VDDIO18
VSS18
VSS83
VCC_CORE
1.8VSUS
1.8VSUS
SMDDR_VTERM
SMDDR_VTERM
L15
T21
C797
.22U
AD8
L14
C356
.1U
C378
.1U
VDD19
VDDIO19
VSS19
VSS84
VCC_CORE
C799
.22U
SMDDR_VTERM
C302
.1U
SMDDR_VTERM
C372
.1U
M2
T23
AD25
L16
VDD20
VDDIO20
VSS20
VSS85
VCC_CORE
M6
T25
1.8VSUS
AE11
L18
VDD21
VDDIO21
VSS21
VSS86
VCC_CORE
1.8VSUS
M8
U17
AE13
M7
VDD22
VDDIO22
VSS22
VSS87
VCC_CORE
1.8VSUS
1.8VSUS
M10
V18
AE15
M9
VDD23
VDDIO23
VSS23
VSS88
VCC_CORE
M16
V21
AE17
M11
VDD24
VDDIO24
VSS24
VSS89
VCC_CORE
1.8VSUS
N7
V23
AE19
M17
VDD25
VDDIO25
VSS25
VSS90
VCC_CORE
N9
V25
1.8VSUS
AE21
N4
VDD26
VDDIO26
VSS26
VSS91
VCC_CORE
1.8VSUS
Layout note: Place one cap close to every 2
pullup resistors terminated to
SMDDR_VTERM
N11
Y25
AE23
N6
VDD27
VDDIO27
VSS27
VSS92
VCC_CORE
P8
B4
N8
VDD28
VSS28
VSS93
VCC_CORE
P10
B6
N10
VDD29
VSS29
VSS94
VCC_CORE
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
C80
4.7UA
P16
A10
B8
N16
VDD30
VTT1
VSS30
VSS95
VCC_CORE
R4
AA10
C725
.22U
B9
N18
VDD31
VTT2
VSS31
VSS96
VCC_CORE
C61
4.7UA
R7
AB10
B11
P2
VDD32
VTT3
VSS32
VSS97
VCC_CORE
C81
4.7UA
C275
.1U
R9
AC10
B13
P7
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
1.8VSUS
1.8VSUS
1.8VSUS
VDD33
VTT4
VSS33
VSS98
VCC_CORE
R11
AD10
C65
4.7UA
B15
P9
VDD34
VTT5
VSS34
VSS99
VCC_CORE
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
C56
.22U
C277
.1U
T2
B10
B17
P11
VDD35
VTT6
VSS35
VSS100
VCC_CORE
T6
C10
C723
.22U
B19
P17
VDD36
VTT7
VSS36
VSS101
VCC_CORE
T8
D10
C57
.22U
B21
R8
C276
.1U
VDD37
VTT8
VSS37
VSS102
VCC_CORE
C54
1000P/X7R
T10
W10
B23
R10
VDD38
VTT9
VSS38
VSS103
VCC_CORE
T12
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
C55
1000P/X7R
B25
R16
VDD39
VSS39
VSS104
VCC_CORE
C719
180PA/50V
B
T14
D6
R18
B
VDD40
VSS40
VSS105
VCC_CORE
C75
180PA/50V
T16
D8
T7
VDD41
VSS41
VSS106
VCC_CORE
U7
C74
180PA/50V
D9
T9
VDD42
VSS42
VSS107
VCC_CORE
SMDDR_VTERM
C718
180PA/50V
U9
D11
T11
VDD43
VSS43
VSS108
VCC_CORE
U11
C60
1000P/X7R
D13
T13
VDD44
VSS44
VSS109
VCC_CORE
SMDDR_VTERM
C59
1000P/X7R
U13
D15
T15
VDD45
VSS45
VSS110
VCC_CORE
U15
D17
T17
VDD46
VSS46
VSS111
VCC_CORE
V6
D19
U4
VDD47
SMDDR_VTERM
VSS47
VSS112
VCC_CORE
V8
D21
U6
VDD48
VSS48
VSS113
VCC_CORE
V10
(0.9VSUS)
D23
U8
VDD49
VSS49
VSS114
VCC_CORE
V12
D25
U10
VDD50
VSS50
VSS115
VCC_CORE
V14
E4
U12
VDD51
VSS51
VSS116
VCC_CORE
V16
F2
U14
VDD52
VSS52
VSS117
VCC_CORE
W4
F11
U16
VDD53
VSS53
VSS118
VCC_CORE
Y2
F13
U18
VDD54
VSS54
VSS119
F15
V2
VSS55
VSS120
F17
V7
AMD S1 SOCKET
VSS56
VSS121
F19
V9
VSS57
VSS122
C392
*4.7UB
F21
V11
1.8VSUS
SMDDR_VTERM
VSS58
VSS123
F23
V13
VSS59
VSS124
C395
*4.7UB
F25
V15
1.8VSUS
SMDDR_VTERM
VSS60
VSS125
H7
V17
VSS61
VSS126
C393
.1U
H9
W6
1.8VSUS
SMDDR_VTERM
VSS62
VSS127
H21
Y21
VSS63
VSS128
C802
.1U
H23
Y23
1.8VSUS
SMDDR_VTERM
VSS64
VSS129
J4
VSS65
C412
.1U
1.8VSUS
SMDDR_VTERM
AMD S1 SOCKET
C
C
DDRII CHANNEL A TERMINATION
DDRII CHANNEL B TERMINATION
M_A_BA1
M_A_A0
RP23
47X2
SMDDR_VTERM
M_A_BA2
RP12
47X2
SMDDR_VTERM
M_B_BA1
RP38
47X2
SMDDR_VTERM
M_B_CS#0
RP39
47X2
SMDDR_VTERM
1
3
2
4
1
3
2
4
1
3
2
4
1
3
2
4
M_A_A12
M_B_A4
M_B_RAS#
3,5
M_B_RAS#
M_A_CS#0
RP16
47X2
M_A_A10
RP15
47X2
M_B_ODT0
RP32
47X2
M_B_A0
RP30
47X2
1
3
2
4
1
3
2
4
1
3
2
4
1
3
2
4
M_A_BA0
M_A_A1
M_B_CS#1
M_B_A10
M_A_WE#
RP17
47X2
M_A_A9
RP13
47X2
M_B_A3
RP29
47X2
M_B_A12
RP27
47X2
1
3
2
4
1
3
2
4
1
3
2
4
1
3
2
4
3,5
M_A_WE#
M_A_ODT1
M_A_A8
M_B_A1
M_B_BA2
M_A_CS#3
RP25
1
3
2
4
47X2
M_A_A11
RP20
1
3
2
4
47X2
M_B_WE#
RP31
1
3
2
4
47X2
M_B_A7
RP36
1
3
2
4
47X2
3,5
M_B_WE#
M_A_ODT0
M_A_A14
M_B_BA0
M_B_A14
M_A_A5
M_A_A7
M_B_A2
M_B_A8
RP14
1
3
2
4
47X2
RP21
1
3
2
4
47X2
RP37
1
3
2
4
47X2
RP28
1
3
2
4
47X2
M_A_A3
M_A_A6
M_B_A6
M_B_A5
M_A_A13
RP24
47X2
M_A_A4
RP22
47X2
M_B_CAS#
RP33
47X2
M_B_CS#2
RP26
47X2
1
3
2
4
1
3
2
4
1
3
2
4
1
3
2
4
3,5
M_B_CAS#
M_A_RAS#
M_A_A2
M_B_ODT1
M_B_A9
3,5
M_A_RAS#
M_A_CS#2
RP11
47X2
M_A_CAS#
RP18
47X2
M_B_CKE1
RP34
47X2
M_B_CS#3
RP40
47X2
1
3
2
4
1
3
2
4
1
3
2
4
1
3
2
4
3,5
M_A_CAS#
M_A_CKE0
M_A_CS#1
M_B_CKE0
M_B_A13
M_A_CKE1
RP19
47X2
M_B_A11
RP35
47X2
1
3
2
4
1
3
2
4
M_A_A15
M_B_A15
D
D
C360
.1U
1.8VSUS
SMDDR_VTERM
C361
.1U
1.8VSUS
SMDDR_VTERM
M_B_A[15..0]
PROJECT : AT8
M_B_A[15..0]3,5
M_A_A[15..0]
M_B_CKE[1..0]
C394
.1U
M_A_A[15..0]3,5
M_A_CKE[1..0]3,5
1.8VSUS
M_B_CKE[1..0]3,5
SMDDR_VTERM
M_A_CKE[1..0]
M_B_ODT[1..0]
Quanta Computer Inc.
M_B_ODT[1..0]3,5
M_A_ODT[1..0]
M_B_BA[2..0]
C413
.1U
M_A_ODT[1..0]3,5
1.8VSUS
M_B_BA[2..0]3,5
SMDDR_VTERM
M_A_BA[2..0]
M_B_CS#[3..0]
M_A_BA[2..0]3,5
M_B_CS#[3..0]3,5
M_A_CS#[3..0]
C411
.1U
1.8VSUS
M_A_CS#[3..0]3,5
SMDDR_VTERM
Size
Document Number
Rev
Custom
CPU(POWER/GND)
1A
NB5/RD2/HW1
Date:
Thursday, December 29, 2005
Sheet
4
of
38
1
2
3
4
5
6
7
8
PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com
1
2
3
4
5
6
7
8
05
M_A_CKE[0..1]
M_A_CS#[0..3]
M_A_RAS#
M_A_CAS#
M_A_WE#
M_A_CLK1
M_A_DQM[0..7]
M_A_DQS[0..7]
M_A_A[15..0]
M_B_CKE[0..1]
M_B_CLK1
M_B_DQM[0..7]
M_A_CKE[0..1]3,4
M_A_CLK13
M_A_DQM[0..7]3
M_A_DQ[0..63]3
M_A_DQS[0..7]3
M_A_A[15..0]3,4
M_B_CKE[0..1]3,4
M_B_CLK13
M_B_DQM[0..7]3
M_A_CLK1#
M_A_DQ[0..63]
M_B_CS#[0..3]
M_B_RAS#
M_B_CLK1#
M_B_DQ[0..63]
M_B_DQS[0..7]
M_B_DQS#[0..7]
M_A_CS#[0..3]3,4
M_A_CLK1#3
M_B_CS#[0..3]3,4
M_B_RAS#3,4
M_B_CAS#3,4
M_B_WE#3,4
M_B_CLK1#3
M_B_CLK23
M_B_DQ[0..63]3
M_A_CLK2
M_B_CLK2
M_B_CLK2#
M_A_CLK23
M_B_DQS[0..7]3
M_A_CLK2#
M_A_DQS#[0..7]
M_A_RAS#3,4
M_A_CLK2#3
M_A_DQS#[0..7]3
M_B_CLK2#3
M_B_ODT[0..1]3,4
M_B_DQS#[0..7]3
M_A_BA[0..2]
M_A_ODT[0..1]
M_B_BA[0..2]
M_B_A[15..0]
M_B_CAS#
M_B_WE#
M_A_CAS#3,4
M_A_BA[0..2]3,4
M_B_BA[0..2]3,4
M_B_A[15..0]3,4
M_B_ODT[0..1]
M_A_WE#3,4
M_A_ODT[0..1]3,4
A
A
M_A_DQ5
M_A_DQ32
M_B_DQ1
M_B_DQ36
5
123
5
123
1
2
1
2
SMDDR_VREF_DIMM
SMDDR_VREF_DIMM
DQ0
DQ32
DQ0
DQ32
VREF
VSS_1
VREF
VSS_1
M_A_DQ1
M_A_DQ36
M_B_DQ4
M_B_DQ37
7
125
7
125
3
3
DQ1
DQ33
DQ1
DQ33
VSS_2
VSS_2
M_A_DQ2
M_A_DQ34
M_B_DQ3
M_B_DQ38
17
135
17
135
8
8
DQ2
DQ34
DQ2
DQ34
VSS_3
VSS_3
M_A_DQ3
19
137
M_A_DQ37
M_B_DQ2
19
137
M_B_DQ34
C832
2.2UA
1.8VSUS
81
9
C805
2.2UA
1.8VSUS
1.8VSUS
81
9
DQ3
DQ35
DQ3
DQ35
VDD_1
VSS_4
VDD_1
VSS_4
M_A_DQ0
M_A_DQ33
M_B_DQ0
M_B_DQ32
C808
2.2UA
1.8VSUS
1.8VSUS
1.8VSUS
C806
2.2UA
4
124
4
124
82
12
82
12
DQ4
DQ36
DQ4
DQ36
VDD_2
VSS_5
VDD_2
VSS_5
M_A_DQ4
M_A_DQ38
M_B_DQ5
M_B_DQ33
C829
2.2UA
C831
2.2UA
1.8VSUS
6
126
6
126
87
15
87
15
DQ5
DQ37
DQ5
DQ37
VDD_3
VSS_6
VDD_3
VSS_6
M_A_DQ6
M_A_DQ39
M_B_DQ7
M_B_DQ39
1.8VSUS
14
134
14
134
C803
.1U
88
18
C825
.1U
88
18
DQ6
DQ38
DQ6
DQ38
VDD_4
VSS_7
VDD_4
VSS_7
M_A_DQ7
M_A_DQ35
M_B_DQ6
M_B_DQ35
C804
.1U
1.8VSUS
C826
.1U
1.8VSUS
16
136
16
136
95
21
95
21
DQ7
DQ39
DQ7
DQ39
VDD_5
VSS_8
VDD_5
VSS_8
M_A_DQ9
23
141
M_A_DQ40
M_B_DQ9
23
141
M_B_DQ44
C375
.1U
1.8VSUS
96
24
C827
.1U
1.8VSUS
96
24
DQ8
DQ40
DQ8
DQ40
VDD_6
VSS_9
VDD_6
VSS_9
M_A_DQ8
M_A_DQ41
M_B_DQ8
M_B_DQ41
C798
.1U
1.8VSUS
C824
.1U
1.8VSUS
25
143
25
143
103
27
103
27
DQ9
DQ41
DQ9
DQ41
VDD_7
VSS_10
VDD_7
VSS_10
M_A_DQ10
M_A_DQ42
M_B_DQ14
M_B_DQ47
C830
.1U
1.8VSUS
C376
.1U
1.8VSUS
35
151
35
151
104
28
104
28
DQ10
DQ42
DQ10
DQ42
VDD_8
VSS_11
VDD_8
VSS_11
M_A_DQ14
37
153
M_A_DQ46
M_B_DQ15
37
153
M_B_DQ46
C374
.1U
1.8VSUS
1.8VSUS
111
33
C377
.1U
1.8VSUS
111
33
DQ11
DQ43
DQ11
DQ43
VDD_9
VSS_12
VDD_9
VSS_12
M_A_DQ13
M_A_DQ44
M_B_DQ12
M_B_DQ40
C380
.1U
C373
.1U
1.8VSUS
20
140
20
140
112
34
112
34
DQ12
DQ44
DQ12
DQ44
VDD_10
VSS_13
VDD_10
VSS_13
M_A_DQ12
22
142
M_A_DQ45
M_B_DQ13
22
142
M_B_DQ45
C810
.1U
1.8VSUS
1.8VSUS
117
39
C828
.1U
1.8VSUS
117
39
DQ13
DQ45
DQ13
DQ45
VDD_11
VSS_14
VDD_11
VSS_14
M_A_DQ15
M_A_DQ43
M_B_DQ10
M_B_DQ42
1.8VSUS
36
152
36
152
118
40
118
40
DQ14
DQ46
DQ14
DQ46
VDD_12
VSS_15
VDD_12
VSS_15
M_A_DQ11
M_A_DQ47
M_B_DQ11
M_B_DQ43
38
154
38
154
41
41
DQ15
DQ47
DQ15
DQ47
VSS_16
VSS_16
M_A_DQ17
43
157
M_A_DQ55
M_B_DQ17
43
157
M_B_DQ55
42
42
DQ16
DQ48
DQ16
DQ48
VSS_17
VSS_17
M_A_DQ21
M_A_DQ16
M_A_DQ54
M_B_DQ20
M_B_DQ54
M_A_ODT0
M_B_ODT0
M_B_ODT1
45
159
45
159
114
47
114
47
DQ17
DQ49
DQ17
DQ49
ODT0
VSS_18
ODT0
VSS_18
M_A_DQ18
55
173
M_A_DQ49
M_B_DQ19
55
173
M_B_DQ53
M_A_ODT1
119
48
119
48
DQ18
DQ50
DQ18
DQ50
ODT1
VSS_19
ODT1
VSS_19
M_A_DQ52
M_B_DQ18
M_B_DQ48
57
175
57
175
53
53
DQ19
DQ51
DQ19
DQ51
VSS_20
VSS_20
M_A_DQ20
M_A_DQ48
M_B_DQ16
M_B_DQ51
44
158
44
158
54
54
DQ20
DQ52
DQ20
DQ52
VSS_21
VSS_21
M_A_DQ19
46
160
M_A_DQ53
M_B_DQ21
46
160
M_B_DQ50
50
59
50
59
DQ21
DQ53
DQ21
DQ53
NC_1
VSS_22
NC_1
VSS_22
M_A_DQ22
M_A_DQ50
M_B_DQ22
M_B_DQ49
56
174
56
174
69
60
69
60
DQ22
DQ54
DQ22
DQ54
NC_2
VSS_23
NC_2
VSS_23
M_A_DQ23
58
176
M_A_DQ51
M_B_DQ23
58
176
M_B_DQ52
M_A_CS#2
83
65
M_B_CS#2
83
65
DQ23
DQ55
DQ23
DQ55
NC_3
VSS_24
NC_3
VSS_24
M_A_DQ24
M_A_DQ57
M_B_DQ24
M_B_DQ57
M_A_A15
M_B_A15
M_B_A13
61
179
61
179
84
66
84
66
DQ24
DQ56
DQ24
DQ56
NC_4/A15
VSS_25
NC_4/A15
VSS_25
M_A_DQ25
M_A_DQ61
M_B_DQ25
M_B_DQ60
M_A_A14
M_A_A13
M_B_A14
63
181
63
181
86
71
86
71
DQ25
DQ57
DQ25
DQ57
NC_5/A14
VSS_26
NC_5/A14
VSS_26
M_A_DQ27
73
189
M_A_DQ63
M_B_DQ30
73
189
M_B_DQ62
116
72
116
72
DQ26
DQ58
DQ26
DQ58
NC_6/A13
VSS_27
NC_6/A13
VSS_27
M_A_DQ30
M_A_DQ62
M_B_DQ31
M_B_DQ59
M_A_CS#3
M_B_CS#3
B
75
191
75
191
120
77
120
77
B
DQ27
DQ59
DQ27
DQ59
NC_7
VSS_28
NC_7
VSS_28
M_A_DQ28
M_A_DQ56
M_B_DQ28
M_B_DQ61
62
180
62
180
163
78
163
78
DQ28
DQ60
DQ28
DQ60
NC_8
VSS_29
NC_8
VSS_29
M_A_DQ29
M_A_DQ60
M_B_DQ29
M_B_DQ56
64
182
64
182
121
121
DQ29
DQ61
DQ29
DQ61
VSS_30
VSS_30
M_A_DQ26
M_A_DQ59
M_B_DQ27
M_B_DQ58
74
192
74
192
122
122
DQ30
DQ62
DQ30
DQ62
VSS_31
VSS_31
M_A_DQ31
76
194
M_A_DQ58
M_B_DQ26
76
194
M_B_DQ63
162
127
162
127
DQ31
DQ63
DQ31
DQ63
VSS_45
VSS_32
VSS_45
VSS_32
165
128
165
128
VSS_46
VSS_33
VSS_46
VSS_33
M_A_A0
M_A_DQM0
M_A_DQM2
M_B_A0
M_B_DQM0
102
10
102
10
168
132
168
132
A0
DM0
A0
DM0
VSS_47
VSS_34
VSS_47
VSS_34
M_A_A1
M_A_DQM1
M_B_A1
M_B_DQM1
101
26
101
26
171
133
171
133
A1
DM1
A1
DM1
VSS_48
VSS_35
VSS_48
VSS_35
M_A_A2
M_B_A2
M_B_DQM2
100
52
100
52
172
138
172
138
A2
DM2
A2
DM2
VSS_49
VSS_36
VSS_49
VSS_36
M_A_A3
99
67
M_A_DQM3
M_A_DQM4
M_B_A3
99
67
M_B_DQM3
177
139
177
139
A3
DM3
A3
DM3
VSS_50
VSS_37
VSS_50
VSS_37
M_A_A4
M_B_A4
M_B_DQM4
98
130
98
130
178
144
178
144
A4
DM4
A4
DM4
VSS_51
VSS_38
VSS_51
VSS_38
M_A_A5
M_A_DQM5
M_B_A5
M_B_DQM5
97
147
97
147
183
145
183
145
A5
DM5
A5
DM5
VSS_52
VSS_39
VSS_52
VSS_39
M_A_A7
94
170
M_A_DQM6
M_B_A6
94
170
M_B_DQM6
184
149
184
149
A6
DM6
A6
DM6
VSS_53
VSS_40
VSS_53
VSS_40
M_A_A6
M_A_DQM7
M_B_A7
M_B_DQM7
92
185
92
185
187
150
187
150
A7
DM7
A7
DM7
VSS_54
VSS_41
VSS_54
VSS_41
M_A_A8
M_A_DQS0
M_B_A8
M_B_DQS0
93
13
93
13
190
155
190
155
A8
DQS0
A8
DQS0
VSS_55
VSS_42
VSS_55
VSS_42
M_A_A9
M_A_DQS#0
M_B_A9
M_B_DQS#0
91
11
91
11
193
156
193
156
A9
DQS0
A9
DQS0
VSS_56
VSS_43
VSS_56
VSS_43
M_A_A10
M_A_DQS1
M_B_A10
M_B_DQS1
105
31
105
31
196
161
196
161
A10/AP
DQS1
A10/AP
DQS1
VSS_57
VSS_44
VSS_57
VSS_44
M_A_A11
90
29
M_A_DQS#1
M_B_A11
90
29
M_B_DQS#1
201
202
201
202
A11
DQS1
A11
DQS1
VSS_58
VSS_59
VSS_58
VSS_59
M_A_A12
M_A_DQS2
M_B_A12
M_B_DQS2
89
51
89
51
A12
DQS2
A12
DQS2
M_A_DQS#2
M_B_DQS#2
49
49
DQS2
DQS2
M_A_BA0
M_A_DQS3
M_B_BA0
M_B_DQS3
107
70
107
70
BA0
DQS3
BA0
DQS3
M_A_BA1
M_A_DQS#3
M_B_BA1
M_B_DQS#3
2-1734073-1
1565917-4
106
68
106
68
BA1
DQS3
BA1
DQS3
M_A_BA2
85
131
M_A_DQS4
M_B_BA2
85
131
M_B_DQS4
CN23B
CN24B
NC/BA2
DQS4
NC/BA2
DQS4
M_A_DQS#4
M_B_DQS#4
129
129
DQS4
DQS4
M_A_CLK1
M_A_DQS5
M_B_CLK1
M_B_DQS5
SO-DIMM BYPASS PLACEMENT :
30
148
30
148
CLK0
DQS5
CLK0
DQS5
M_A_CLK1#
M_A_DQS#5
M_B_CLK1#
M_B_DQS#5
32
146
32
146
CLK0
DQS5
CLK0
DQS5
M_A_DQS6
M_B_DQS6
Place these Caps near So-Dimm1.
3V
169
169
3V
2,7,8,9,10,11,15,16,17,18,19,23,26,27,28,29,30,32,33,35,36,38
DQS6
DQS6
M_A_CLK2
164
167
M_A_DQS#6
M_B_CLK2
164
167
M_B_DQS#6
1.8VSUS
CLK1
DQS6
CLK1
DQS6
1.8VSUS2,3,4,32,36,37
M_A_CLK2#
M_A_DQS7
M_B_CLK2#
M_B_DQS7
166
188
166
188
No Vias Between the Trace of PIN to CAP.
CKL1
DQS7
CKL1
DQS7
M_A_DQS#7
M_B_DQS#7
186
186
C
DQS7
DQS7
C
DDR_SMBCLK
DDR_SMBCLK
197
197
SCL
SCL
DDR_SMBDTA
M_A_CS#0
DDR_SMBDTA
M_B_CS#0
195
110
195
110
SDA
CS0
SDA
CS0
DIM1_SA0
DIM1_SA1
198
115
M_A_CS#1
DIM2_SA0
198
115
M_B_CS#1
SMDDR_VREF_DIMM
SMDDR_VREF_DIMM :
TRACE WIDTH > 20 MIL
PUT BYPASS CAP ON EACH DIMM
SA0
CS1
SA0
CS1
SMDDR_VREF
M_A_RAS#
DIM2_SA1
M_B_RAS#
R127
*0R
200
108
200
108
SA1
RAS
SA1
RAS
M_A_CAS#
M_B_CAS#
R128
2KF
113
113
1.8VSUS
CAS
CAS
M_A_WE#
M_B_WE#
199
109
199
109
R123
2KF
3V
VDDSPD
WE
3V
VDDSPD
WE
M_A_CKE0
M_B_CKE0
79
79
CKE0
CKE0
80
M_A_CKE1
80
M_B_CKE1
C382
.1U
SMDDR_VREF_DIMM
SMDDR_VREF_DIMM
C370
.1U
CKE1
CKE1
C308
2.2UA
C388
2.2UA
CKE 0,1
CKE 2,3
2-1734073-1
H 9.2
1565917-4
H 5.2
CN23A
CN24A
R138
10K
DIM1_SA0
DIM2_SA0
DIM2_SA1
R150
10K
C396
.1U
3V
3V
C384
2.2UA
R139
10K
DIM1_SA1
R151
10K
C311
2.2UA
C309
.1U
3V
SMbus address A0
SMbus address A4
Close DDR2 socket
3V
U33
DDR_SMBDTA
DDR_SMBDTA
DDR_SMBCLK
R141
2.2K
1
3
3V
CGDAT_SMB17
C801
*.1U
7
8
A0
+VS
Q13
2N7002E
R135
2.2K
6
3V
A1
D
5
D
A2
3
DIMM_THEM#
O.S
DIMM_THEM#2
3V
LM86_SMD
LM86_SMC
1
2
LM86_SMD
SDA
2
4
2
LM86_SMC
SCL
GND
Address:92h
PROJECT : AT8
3
1
DDR_SMBCLK
17
CGCLK_SMB
*G751
(LM75CIMM3)
Quanta Computer Inc.
Q12
2N7002E
R537
*10K
DIMM_THEM#
3V
Size
Document Number
Rev
Custom
CPU(MEM/IF)
1A
3V
NB5/RD2/HW1
Date:
Thursday, December 29, 2005
Sheet
5
of
38
1
2
3
4
5
6
7
8
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