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Power Management
Texas Instruments Incorporated
Texas Instruments Incorporated
Designing a linear Li-Ion battery charger
with power-path control
By Charles Mauney
Senior Systems/Applications Engineer,
Battery Management and Charging Solutions
In theory, a linear battery charger with a sepa-
rate power path for the system is a fairly simple
design concept and can be built with an LDO
adjusted to 4.2 V; a current-limit resistor; three
p-channel FETs to switch the system load
between the input power and the battery source;
and some bias parts. In reality, there is much
more to a good design than the basic topology.
This article will discuss dynamic power-path
management (DPPM) and explore safety features
that turn a basic topology into a complete design.
The DPPM topology is shown in Figure 1 and
has two power-source pins,V
IN
and V
BAT
. The
charger can be programmed for either a USB
input or an adapter input. The design concept is
to always power the system if power is available,
either from V
IN
or V
BAT
, unless the system is pro-
grammed to shut down. The input FET regulates
the output voltage and will also limit the input
current to the programmed level if the load is
excessive. The battery FET has control loops
associated with charging the
battery and allowing the
battery to power the system.
The input controls and bat-
tery controls act indepen-
dently and are discussed in
more detail later.
Figure 2 shows a charger
solution with a discrete
power path. The LDO pro-
vides the regulated output
voltage, and the input-
current-limit resistor limits
the maximum current that
can be delivered to the bat-
tery. D1, R1, R4, and Q1
monitor the input voltage and
turn on Q2 and Q3 if input
source power is present,
connecting the input to the
system load. If input source
power is not present, Q5 and
Q4 are biased on so the bat-
tery will provide power to the
system load. This state will
hereinafter be referred to as
“battery-supplement mode.”
Figure 1. Power-path topology of battery charger
Adapter or
USB Input
Internal to IC
Q1
V
OUT
V
IN
Q2
Charger
Control Loops,
Logic, and
Drives
R
System
V
BAT
Program Input for USB or
Adapter Current Sense
on Input, Input Control Loops,
and Drives
Battery
GND
GND
1
Figure 2. Discrete charger with battery-supplement mode
R
Limit
4.2 VDC
V
IN
V
OUT
LDO
Adj.
R5
Q2
Q3
V
IN+
Input
Source
(
VDC
)
R2
R3
D1
Zener
Q4
GND
R
System
R7
R4
Q5
Q1
R6
Battery
R1
1
12
12
High-Performance Analog Products
High-Performance Analog Products
www.ti.com/aaj
www.ti.com/aaj
2Q 2009
2Q 2009
Analog Applications Journal
Analog Applications Journal
Texas Instruments Incorporated
Power Management
This charger solution is simple and discrete
but has many limitations and few safety features.
Adding any safety feature will quickly drive up
the solution cost but often may offset the liabil-
ity cost of an unprotected design. LDOs are typ-
ically not highly accurate regulators, especially
with external programmable resistors. If the
regulation was set lower to ensure that the maxi-
mum battery voltage was not exceeded, the typ-
ical voltage and capacity would be lower. The
crude current-limit resistor would allow more
current at lower battery voltages and would not
provide a conditioning current to help recover
depleted cells or to prevent cell damage from
excessive charging.
Typical integrated application
Figure 3 shows the Texas Instruments (TI)
bq24075, a charger with a highly integrated
power path in a 3 × 3-mm, 16-pin QFN package.
The only external components required are two
external programming resistors and three capaci-
tors for the power sources.
Programmed input-source protection
The input-current limit is programmed with the
EN1/2 pins to one of four states: 100 mA, 500 mA,
ILIM, or Suspend, as shown in Figure 4. A resistor can be
used to program ILIM at any level up to the device’s maxi-
mum input current. When current-limited, the input FET
restricts the current to the OUT pin, causing the system
voltage to drop to the DPPM threshold or to the battery
voltage where the charge current will be reduced. Assum-
ing that the protection was designed for the applied
Figure 3. Typical integrated application with
bq24075 charger
1 k
1 k
7
9
PGOOD
CHG
bq24075
Vto
System
OUT
13
IN
OUT
10
11
V
IN
1 µF
4.7 µF
EN2
5
8
VSS
V
BAT
2
3
System
On/Off
Control
15
SYSOFF
4.7 µF
Temp
Pack+
TS
CE
TMR
EN1 ILM
ISET
+
–
4
14
6
12
16
1.18 k
1.13 k
Pack–
source, this feature solves the problem of the system
overloading the adapter or the USB source, which could
potentially damage the source or device. More power-
management details are presented later under “DPPM
protection of output voltage.”
If a current-limited source such as a weak or wrong
adapter or USB is used, the adapter and system voltages
Figure 4. Input-FET control loops
bq24075
Q1
IN
OUT
EN2
Short
Detect
–
V
IN_Low
+
USB 100 mA
USB 500 mA
–
ILIM
V
REF_ILIM
USB Suspend
+
+
EN2
EN1
V
OUT_Reg
–
Charge Pump
13
Analog Applications Journal
2Q 2009
www.ti.com/aaj
High-Performance Analog Products
Power Management
Texas Instruments Incorporated
will drop, causing the IC to enter DPPM mode or battery-
supplement mode. Basing DPPM on the output voltage
solves most loading issues by reducing the charge current,
giving priority to the system load, and allowing operation
with a weak power source or minor AC brownouts. Other
input-current-management solutions without DPPM would
not detect the weak source or reduce the charging current,
and the system would crash.
The V
IN_Low
input loop provides additional protection for
a weak source when in USB 100/500-mA mode. This loop
monitors the voltage on the USB input pin; and, if it drops
to ~4.5 V, Q2 enters its linear range to keep the USB input
voltage from dropping any further, as shown in Figure 5.
This voltage loop is independent of the input-current-limit
loop. This feature adds protection for the USB host in the
event that it cannot deliver the load current because of a
weak source or failed communication. In Figure 5, I
OUT
starts with no load and, at ~250 mA, the current limit of
the weak source causes the source voltage to fall to 4.5 V,
where the V
IN_Low
loop kicks in and the system output
voltage drops about 100 mV to the DPPM threshold. The
charge current is reduced as the load is increased to main-
tain the input at 4.5 V. As the load is reduced, the system
returns to normal operation.
DPPM protection of output voltage
The output voltage powering the system will drop if the
system load current and the battery charge current
exceed the available input current. The input current can
be restricted by the source, the V
IN_Low
loop, or the input-
current-limit setting of the IC. If the output voltage drops
to the DPPM threshold, the charge current will be reduced
to keep the voltage from further decay. This allows the use
of a less expensive adapter because the charging current
is reduced during peak loads.
If the system current exceeds the available input current,
the output voltage will drop to the battery voltage and
enter battery-supplement mode, in which the battery FET
turns on and supplements the input current going to the
system. This allows use of the battery to supplement large
current pulses to the system, which the charger is not
capable of supplying. Figures 6 through 8 show the wave-
forms of the TI bq24072/3/4/5 where the output voltage
drops first into DPPM mode and then into battery-
supplement mode.
Figure 6 shows the waveforms of the bq24072 with V
OUT
initially regulated to about 225 mV above the battery volt-
age. Upon reaching the input-current limit after the first
load step, the IC enters DPPM mode, which reduces the
charge current to keep the output voltage from dropping
below the DPPM threshold. After the second load step,
the system load is greater than the input limit. The output
voltage drops to just below the battery voltage, and the
battery FET turns on and supplements the input current to
the system load. Note that the voltage transitions between
modes are very small and are best for applications that are
sensitive to voltage changes.
Figure 5. V
IN_Low
USB protection with source-
current limit at 250 mA
Figure 6. bq24072 DPPM and battery-
supplement modes with V
B AT
≈
3.1 V
V
(
1 V/div
)
IN
(
1 V/div
)
V
IN
DPPM Mode
Battery-
Supplement
Mode
V
(
1 V/div
)
OUT
V
(1 V/div)
DPPM Mode
OUT
I
(1A/div)
BAT
(
1A/div
)
I
I
(
1A/div
)
BAT
OUT
1
1
V
OUT
= 3.325 V
3
V
~
3.1 V
I
(
1A/div
)
OUT
BAT
DPPM at 3.225 V
Time(100 ms/div)
Time (200 ms/div)
14
High-Performance Analog Products
www.ti.com/aaj
2Q 2009
Analog Applications Journal
Texas Instruments Incorporated
Power Management
The waveforms of the bq24073/4 in Figure 7 were gen-
erated under the same conditions as for the bq24072 in
Figure 6, except that the bq24073/4 regulates V
OUT
at
4.4 V and the DPPM threshold at 4.3 V. Upon entering
battery-supplement mode, the output voltage drops to just
below the battery voltage; so the lower the battery voltage
is, the larger the drop. For an application sensitive to sys-
tem voltage drops, the system load should not exceed the
available input current in order to stay out of battery-
supplement mode. An alternative is to use the bq24072.
The bq24075 waveforms in Figure 8 were generated
under the same conditions as for the bq24072 in Figure 6,
except that the bq24075 regulates V
OUT
at 5.5 V and the
DPPM threshold at 4.3 V. The transition between modes is
larger and dependent on the input voltage and battery volt-
age. If the input voltage is less than 5.5 V, then the regula-
tor is switched fully on to deliver what voltage is available.
Protection from shorting system V
OUT
Shorting the V
OUT
pin can cause excessive current from
the battery or the V
IN
power source. Battery short-circuit
protection disables the battery FET if the voltage drop
from V
BAT
to V
OUT
is greater than 250 mV for a duration
longer than the specified deglitch time. The battery FET is
turned on periodically to check whether the short is still
present, and this hiccup mode will continue until the short
is removed. This prevents damage to the IC and solves
reliability issues.
For V
IN
protection, the input FET limits the input current
to 100 mA when the output voltage is less than 1 V. Once
the excessive load is removed, the output will charge above
1 V and start delivering the programmed input current.
This feature reduces the power dissipation during the out-
put short, which also improves reliability. Figure 9 shows
the waveforms of an output short and the IC’s recovery.
Figure 9 shows the waveforms that occur when the
bq24072’s output is shorted, causing the battery FET and
input FET to turn off. The input source supplies about
90 mA to the output via the input control loop; and,
approximately every 64 ms, the battery FET is turned on
for 250 µs to check whether the short is still present.
Picking the right charger IC
The bq24072/3/4/5 ICs all charge a single-cell Li-Ion battery
properly, but they have various values for the overvoltage-
protection (OVP) threshold, the V
OUT
regulation, and the
DPPM threshold (see Table 1). Each IC also has an
Figure 8. bq24075 DPPM and battery-
supplement modes with V
OUT
= 5.5 V
(
2 V/div
)
V
OUT
V
(
2 V/div
)
Battery-
Supplement
Mode
BAT
DPPM Mode
1
I
(1A/div)
I
(1A/div)
OUT
BAT
3
V
OUT
= 5.5 V
DPPM at 4.3 V
Time
(
100 ms/div
)
Figure 9. Output short-circuit protection
(
2 V/div
)
V
OUT
(
2 V/div
)
V
BAT
1
Hiccup
Status
Check
V Short
Circuit Starts
OUT
Figure 7. bq24073/4 DPPM and battery-
supplement modes with V
OUT
= 4.4 V
(
1A/div
)
I
BAT
V
(2 V/div)
BAT
3
(
1A/div
)
I
OUT
V
(2 V/div)
OUT
Battery-Supplement
Mode
Time
(
20 ms/div
)
DPPM Mode
1
Table 1. Differences between bq24072/3/4/5 ICs
I
(1A/div)
OUT
I
(1A/div)
OPTIONAL
FUNCTION
BAT
DEVICE
V
OVP
V
OUT
V
DPPM
3
bq24072
6.6 V
V
BAT
+ 225 mV
V
O(REG)
– 100 mV
TD
V
OUT
= 4.4 V
DPPM at 4.3 V
bq24073
6.6 V
4.4 V
V
O(REG)
– 100 mV
TD
bq24074
10.5 V
4.4 V
V
O(REG)
– 100 mV
ITERM
Time
(
100 ms/div
)
bq24075
6.6 V
5.5 V
4.3 V
SYSOFF
15
Analog Applications Journal
2Q 2009
www.ti.com/aaj
High-Performance Analog Products
Power Management
Texas Instruments Incorporated
optional control function such as termination
disable (TD), programmable termination
current (ITERM), or system off (SYSOFF).
The 10.5-V OVP is for a nonregulated 5-V
adapter where the unloaded source is above
6.6 V. To minimize power dissipation, during
fast charge the optimum input voltage
should be between 4.5 and 5.5 V.
The bar chart in Figure 10 shows graphi-
cally how the charger output voltage changes
from one operational mode to another for
each charger. If the system is sensitive to
changes in the output voltage and the peak
system load exceeds the input current, the
bq24072 minimizes these changes since it
regulates the output voltage to within 225 mV
of the battery voltage. The bq24073/4 regu-
lates the output voltage to 4.4 V and the
DPPM threshold to 4.3 V. Depending on the
battery voltage, the voltage drop can be large
when the charger enters battery-supplement
mode. The bq24075 regulates the output
voltage to 5.5 V for inputs greater than 5.5 V
and passes through lower voltages. If the
charger output current plus the charge
current exceed the input current, the output
voltage will drop much more than 100 mV,
as shown in Figure 10. A further increase in
output current may put the device in
battery-supplement mode, where another
large drop will occur.
Figure 11 shows the efficiency of the
power topology. Efficiency for a linear
topology is
Figure 10. Output voltage with changes in operational mode
and part number (V
IN
= 5 V)
5
Normal Mode
DPPM Mode
Battery-Supplement
Mode
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
bq24072
bq24073/4
bq24075
Figure 11. System efficiency with changes in operational
mode and part number (V
IN
= 5 V. For V
OUT
, see Figure 10.)
100
Normal Mode
DPPM Mode
Battery-Supplement
Mode
90
VV
V
−
80
IN
OUT
η=
×
100.
IN
70
Each charger mode has an efficiency factor.
For the bq24072/3/4/5, the efficiency during
battery-supplement mode is the same given
the same input voltage and battery voltage.
The bq24072 has the least change in
output voltage between modes, but the
efficiency drops as the battery discharges.
The bq24073/4 is more efficient in normal
and DPPM modes but may have a larger
internal voltage drop upon entering battery-
supplement mode. The bq24075 has high
efficiency in normal mode and good effi-
ciency in DPPM mode, but it may have a
large change in output voltage after switch-
ing from normal to DPPM to battery-
supplement mode.
The decision for the designer is whether the charger
should be sensitive to system voltage changes, have lower
efficiency, or both. If the charger is sensitive to voltage
changes, will the system operations cause changes between
60
50
40
30
20
10
0
bq24072
bq24073/4
bq24075
the modes with large voltage steps? Because of the low
power drain from the adapter or USB source, efficiency is
not typically a cost concern, but it can be a heat-dissipation
issue in the device.
16
High-Performance Analog Products
www.ti.com/aaj
2Q 2009
Analog Applications Journal
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