slyt222.pdf

Texas Instruments Incorporated

Data Acquisition

Operating multiple oversampling

data converters

By Joe Purvis (Email: j-purvis1@ti.com)

Data Acquisition Products

The secret is in the timing

Frequently it’s important to arrange or predict a series of

events in order to achieve a successful result. A nontrivial

example is that of a pedestrian safely crossing a busy road.

In this case the pedestrian may have to perform a number

of estimated measurements in parallel. The speed and

direction of any cars, for example, should be monitored

throughout the process until the pedestrian safely reaches

the other side of the road. The technique in this case is

essentially to ensure that the pedestrian’s x, y, and t coordi-

nates do not correspond to any vehicle’s x, y, and t coordi-

nates. If all three coordinates were the same, then the

pedestrian would have a problem.

Similarly, in many control situations it is often essential

to know the value of more than one property of an event

at a specific instant in time. When various values of a

property need to be known concurrently, this is typically

referred to as “simultaneous sampling.”

For example, in seismic applications, the vibrations from

controlled explosions can be sensed and measured.

Vibrations in the x, y, and z planes should be recorded at

the same time for more precise measurements and simpler

data analysis.

Elsewhere, it may be important to monitor the same

physical variable simultaneously. For example, in automo-

bile braking systems it’s important to measure the torque

for each wheel to enable the car’s onboard computer to

decide if the car is skidding and what appropriate action

to take.

A final example where simultaneous sampling is useful

is in spacecraft sensors. The Galileo spacecraft, for

instance, launched a probe into the Jovian atmosphere in

September 2003. The probe had around 60 minutes to make

its measurements and transmit data before the extreme

atmospheric pressures crushed it. As the spacecraft

descended, it was important to know the depth to which it

had descended and at the same time the pressure being

exerted upon it, the outside temperature, and perhaps the

magnetic field strength.

Oversampling trap

Oversampling data converters generally have better ac and

dc specifications than those based on a successive approx-

imation register (SAR). But SAR converters do have one

fundamental advantage; namely, on command from the

host, they can complete and deliver one measurement.

By comparison, oversampling architectures rely upon

averaging repeated coarse measurements before arriving

at a final value. The architecture details are beyond the

scope of this article, but it’s essential to appreciate this

point to successfully use oversampling converters.

Seeing double

The Oxford English Dictionary’s definition of “simultaneous”

is given as “occurring, existing or operating at the same

time.” However, this definition is unsatisfactory in real

applications. Typically, in the real world, the user may

want to measure two, three, or more properties of an

event within the same space of time. Doing this, as with

any time-domain data conversion, quantizes the continuous

analog value into a series of discrete data values. However,

it also quantizes the measurements to specific instants of

time. This is the “space of time” that the user determines

is adequate for the purpose of the measurements to be

made. In oversampling systems, time quantization is deter-

mined by the MCLK used. Later in the conversion process,

through various averaging processes, the data rate is

essentially slowed down.

Data transfer principles

The preliminary details in support of this article are con-

tained in Reference 1. It is recommended that the reader

should first read this application report to gain an under-

standing of the device’s operation.

Modulator clock (MCLK)

The MCLK applied to the ADS1252 ADC is the principal

driver used to set the characteristics of the ADC. The two

properties that MCLK provide are the frequency response

of the ADC and the frequency at which the ADC indicates

that new data is available.

The MCLK period (τ MCLK ) is defined as

τ MCLK

(1)

MCLK

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Analog and Mixed-Signal Products

Data Acquisition

Texas Instruments Incorporated

Figure 1. DRDY and DOUT phases of MCLK cycle

DOUT Mode

DRDY Mode

DOUT Mode

DRDY Mode

t 4

t 2

t 3

Data

DOUT/DRDY

t 1

Digital interface

To briefly recap the operation of the digital interface from

the datasheet, there is only one data output pin. T he fun c-

tion of this pin is multiplexed between DOUT and DRDY.

A complete conversion consumes 384 MCLK cycles. The

cycle is divided into two phases (Figure 1) .

The first phase of the cycle is known as DRDY mode.

Follow ing the t DOUT time, the rising edge of the

DOUT/DRDY signal indicates that new data will be avail-

able in 36 MCLK cycles. During this time the data output

rupt pin on the host system.

The second phase of the cycle is known as DOUT mode.

During this time the user can safely read the converted

data at a clock rate determined by the shift clock (SCLK).

• The data stored within ADC2 is clocked out of the

device with a dedicated SCLK signal, SCLK2. During

this time SCLK1, SCLK3, SCLK4, and SCLK5 should

remain LOW (inactive).

• The data stored within ADC3 is clocked out of the

device with a dedicated SCLK signal, SCLK3. During

this time SCLK1, SCLK2, SCLK4, and SCLK5 should

remain LOW (inactive).

• The data stored within ADC4 is clocked out of the

device with a dedicated SCLK signal, SCLK4. During

this time SCLK1, SCLK2, SCLK3, and SCLK5 should

remain LOW (inactive).

• The data stored within ADC5 is clocked out of the

device with a dedicated SCLK signal, SCLK5. During

this time SCLK1, SCLK2, SCLK3, and SCLK4 should

remain LOW (inactive).

To provide a coherent basis within which the measure-

ments are made, all the ADCs share the same MCLK. This

provides two important advantages:

• It requires that the measurements from all ADCs be

made within the same duration of time (simultane-

ously sampled).

• It provides the user with confidence in knowing

exactly when data from any ADC is available. In a

multiple-ADC system this is significant, since we can

be certain that when data is signaled as available for

any ADC it will be available for all ADCs. The conse-

quence of this is that the system and software can be

simplified by connecting only one interrupt pin and

writing only one interrupt service routine to read data

from 5 converters.

Discussion of a 5-ADC system

Let’s consider a system that requires 5 variables to be

measured simultaneously. We can summarize what this

situation would look like over 2 complete cycles, as shown

in Table 1.

The op eration can be described as follows:

1. DRDY mode—The first rising edge of DOUT/DRDY indi-

cates that new data will be available in 36 MCLK cycles.

2. DOUT mode—Since there are 5 ADCs in this example,

the data from each of these devices must be read

sequentially.

• The data stored within ADC1 is clocked out of the

device with a dedicated SCLK signal, SCLK1. During

this time SCLK2, SCLK3, SCLK4, and SCLK5 should

remain LOW (inactive).

Table 1. Measuring 5 variables simultaneously

2 CONVERSION CYCLES

1 CONVERSION CYCLE

MODE

DRDY

DOUT

DRDY

DOUT

36 MCLKs

348 MCLKs

36 MCLKs

348 MCLKs

ADC1

ADC2

DRDY

ADC3

DRDY

ADC3

ADC4

ADC5

Analog Applications Journal

Analog and Mixed-Signal Products

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4Q 2005

Texas Instruments Incorporated

Data Acquisition

An additional benefit of this architecture is that, since

all ADCs complete a conversion at the same time, the host

system can choose to read the data in any particular order.

In some cases it might read data sequentially, starting with

ADC1 data and ending with ADC5 data. In some cases it

might read data in reverse order; and perhaps in some

other situations it might always read data from ADC1,

ADC2, and ADC3 data but read ADC4 and ADC5 data only

under special circumstances.

For example, if τ SCLK = 500 ns, then 24 × τ SCLK = 12 µs,

for 24 bits of data. This indicates that it will take at least

12 µs to clock the data out of any ADC (this sets t DOUT ).

Consequently, if there are 5 ADCs sampling data synchro-

nously, it will take at least 5 × 12 µs (60 µs) until the system

can read the first ADC again.

Therefore, according to Equation 2, the maximum

MCLK will be 5.8 MHz.

This reasoning can sometimes become clearer if we con-

sider the contrary position. For instance, in the preceding

example, if the MCLK is faster than 5.8 MHz—say, 10 MHz

—this means that t DOUT is 34.8 µs (348 × 100 ns). If, dur-

ing this time, 5 ADCs are expected to send data to a host

system, each ADC can send data for only 6.96 µs. So each

ADC has 6.96 µs to transfer 24 bits of data. If one bit of data

is transmitted on successive SCLK edges, then

A tale of 2 clocks

Regard less of the number of ADCs, the same principle of

DOUT/DRDY time must still be adhered to for the ADS1252.

In general, for n data converters, the time allocated for

DOUT mode can be expressed in seconds as

348

τ SCLK =

6.96 µs/24 = 290 ns; therefore, SCLK is 1/τ SCLK = 3.45 MHz.

Since the SCLK frequency sourced by the SPI ports of

many microprocessors is limited to around 2 MHz, it is an

important parameter to check in the host system’s specifi-

cation during the design phase.

The ADS1252 can support SCLK rates of up to 16 MHz.

Slowing things down

Considering the case when MCLK is 32.768 kHz, we can

determine t DOUT and SCLK as given in Table 3, since

τ MCLK is now 30.5 µs.

The software example given in this article is for a 2-ADC

system using a 32.768-kHz modulator.

MCLK

(2)

DOUT n

()

The maximum MCLK for the ADS1252 is specified as

16 MHz. Therefore

τ MCLK is 62.5 ns, and t DOUT can be

rewritten in seconds as

−

21 75

(3)

DOUT ()

As the number of ADCs sharing the same MCLK

increases while the DRDY period stays the same, the data

from each ADC must be accessed faster.

Table 2 indica tes ho w fast SCLK must be to keep pace

with the DOUT/DRDY cycle.

Table 2 . SCLK speed required to keep pace with

DOUT/DRDY cycle

Table 3. Determination of t DOUT and SCLK when MCLK

is 32.768 kHz

NUMBER OF ADCs

t DOUT (µs)

SCLK (MHz)

NUMBER OF ADCs

t DOUT (ms)

SCLK (µs)

21.750

1.1

10.61

442.1

10.875

2.2

5.31

221.3

7.2500

3.3

3.53

147.1

5.4375

4.4

2.65

110.4

4.3500

5.5

2.12

88.3

To receive the complete 24 bits from each ADC requires

3 × 8-bit accesses, or 24 SCLKs in total. Therefore, to be able

to access the data from 5 ADCs requires a time of 5 × 24

SCLKs. It is the user’s responsibility to ensure that all

accesses are complete before the next DRDY time begins.

An alternative approach would be to verify the maxi-

mum speed offered by the host system for SCLK (for

example, 2 MHz) and then determine how long it would

take to transfer 24 bits of data at that clock speed. This

would determine the maximum MCLK frequency that

could be used. In a multiple ADC system, if the MCLK is

faster than the calculated maximum, there will not be

enough time for the host to re ad the data before the ADC

switches from DOUT mode to DRDY mode.

HPA449

The HPA449 development card is available directly from

Softbaugh ( www.softbaugh.com) . This MSP430 evaluation

board allows you to experiment with TI data acquisition

products using the MSP430F449.

The MSP430F449 possesses two SPI ports. Both these

ports are mapped and available for use on the HPA449.

This structure makes it easy to demonstrate the principles

of using oversampling converters to design a 2-ADC system.

However, the principles can be scaled to more than 2 ADCs

as previously discussed.

Analog Applications Journal

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Analog and Mixed-Signal Products

Data Acquisition

Texas Instruments Incorporated

Figure 2 shows the block diagram of the system. Notice

that only one interrupt pin is required regardless of the

number of ADCs connected in parallel. Since all ADCs share

the same M CLK, t hey will all provide the same character-

istic DOUT/DRDY signal at the same time. All the HPA449

requires is an indication of when the data is available; it’s

then up to the MSP430 and the software to schedule when

to read the data.

Figure 3 is a composite of two adjacent screen captures

showing CLKX_A, DR_A, CLKX_B, and DR_B.

Summary

This article has discussed some of the important factors to

consider when oversampling data converters are used to

design a simultaneously sampling system.

For this type of design to be successful, the MCLK for

each ADC must be shared. This assures that each converter

is truly sampling the inputs concurrently. It also has the

added benefits of simplifying the digital interface, since

only one interrupt pin is required regardless of the num-

ber of ADCs in the system.

However, a significant limitation is that there is a fixed

amount of time available—348 MCLK periods—to read the

converted data. After this fixed time, the data output reg-

ister is updated with a new data word regardless of

whether or not the data has been read.

The converted data is read from the device with an

SCLK generated via the host system. There is no direct

relationship between MCLK and SCLK, but the user

should be aware that if the data is not shifted out of the

ADC quickly enough, t DOUT time will expire and the data

read back will be a meaningless mixture of old and new

data. This should be carefully considered, particularly

where multiple ADCs are concerned.

Finally, a simple 2-ADC example using t he MSP430 was

presented, showing that the DOUT/DRDY modes for both

ADCs are identical when the same MCLK is used. Simply

ensuring that only one SCLK signal at a time is active arbi-

trates for which ADC sends data back to the microcontroller.

Figure 2. Block diagram of 2-ADC system using MSP430F449

MSP430F449

Port 2

INT_A

Bit 2

Serial Site A

Port 3

CLKX_A

UCLK0

Pin 3

Bit 3

DR_A

SOMI0

Pin 13

Bit 2

INT_A

SIMO0

Pin 15

Bit 1

Serial Site B

Port 4

CLKX_B

UCLK1

Pin 3

Bit 5

DR_B

SOMI1

Pin 13

Bit 4

INT_B

SIMO1

Pin 15

Bit 3

Analog Applications Journal

Analog and Mixed-Signal Products

www.ti.com/aaj

4Q 2005

Texas Instruments Incorporated

Data Acquisition

Figure 3. C ompo site of two adjacent screen captures showing

identical DRDY modes for ADCs using the same MCLK

Data from the

second ADC is

clocked out here

The interrupt to the

host occurs here

Data from the first ADC

is clocked out here

CLKX_A

DR_A

CLKX_B

DR_B

Sin ce both ADCs are supplied with the same MCLK,

the

DRDY

mode for both converters is identical

Reference

For more information related to this article, you can down-

load an Acrobat Reader file at www-s.ti.com/sc/techlit/

litnumber and replace “litnumber” with the TI Lit. # for

the materials listed below.

Document Title

Related Web sites

dataconverter.ti.com

www.ti.com/sc/device/ partnumber

Replace partnumber with ADS1251, ADS1252, or

MSP430F449

www.softbaugh.com

TI Lit. #

1. “Interfacing the ADS1251/52 to the

MSP430F449,” Application Report . . . . . . . . . . .slaa242

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Analog and Mixed-Signal Products

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