slyt413.pdf

Texas Instruments Incorporated

Data Acquisition

The IBIS model, Part 3: Using IBIS models

to investigate signal-integrity issues

By Bonnie C. Baker

Senior Applications Engineer

This article is the third of a three-part series on using a

digital input/output buffer information specification (IBIS)

simulation model during the development phase of a

printed circuit board (PCB). Part 1 discussed the funda-

mental elements of IBIS simulation models and how they

are generated in the SPICE environment. 1 Part 2 discussed

IBIS model validation. 2 The IBIS model brings a simple

solution to many of the signal-integrity problems that may

be encountered during the design phase. This article,

Part 3, shows how to use an IBIS model to extract impor-

tant variables for signal-integrity calculations and PCB

design solutions. Please note that the extracted values are

an integral part of the IBIS model.

Signal-integrity problems

When looking at a digital signal at both ends of a transmis-

sion line, the designer may be surprised at the result of

driving the signal into a PCB trace. Over relatively long

distances, electric signals act more like traveling waves

than instantaneous, changing signals. A good analogy that

describes electric-wave behavior on a circuit board is waves

in a pool. A ripple travels smoothly across the pool because

one volume of water has the same “impedance” as the next.

However, the pool wall presents a very different impedance

and reflects the wave in the opposite direction. Electric

signals injected into a PCB trace experience the same

phenomena, reflecting in a similar manner when imped-

ances are mismatched. Figure 1 shows a PCB setup with

mismatched termination impedances. A microcontroller,

Figure 1. PCB setup with mismatched termination impedances

MSP430 TM

ADS8326

Clock

Data

t CVC

CS/SHDN

Power Down

Sample

Conversion

t SVCS

DCLOCK

t CSD

Use positive clock edge for data transfer

High Impedance

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

D OUT

(MSB)

(LSB)

t CONV

t SMPL

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the Texas Instruments (TI) MSP430™, transmits a clock

signal to the TI ADS8326 ADC, which sends the conver-

sion data back to the MSP430. Figure 2 shows the reflec-

tions created by the impedance mismatches in this setup.

These reflections cause signal-integrity problems on the

transmission lines. Matching the electrical impedance of

the PCB trace at one or both ends can reduce reflections

dramatically.

To tackle the issue of matching a system’s electrical

impedances, the designer needs to understand the imped-

ance characteristics of the integrated circuits (ICs) and

the PCB traces that function as a transmission line. Know-

ing these characteristics allows the designer to model the

connecting elements as distributed transmission lines.

Transmission lines service a variety of circuits, from

single-ended and differential-ended to open-drain output

devices, etc. This article focuses on a single-ended trans-

mission line where the driver has a totem-pole design.

Figure 3 shows the elements to use to design this example

transmission line.

The following IC pin specifications are also needed:

• Transmitter’s output resistance, Z T (W)

• Transmitter’s rise time, t Rise , and fall time, t Fall (seconds)

• Receiver’s input resistance, Z R (W)

• Receiver pin’s capacitive value, C R_Pin (F)

These specifications are usually not available in the IC

manufacturer’s product datasheets. As this article will

demonstrate, all of these values can be pulled from the

IC’s IBIS model in the process of designing the PCB and

using the model to simulate the PCB’s transmission lines.

Figure 2. Induced reflections from mismatched

termination impedances in Figure 1

Cross-

talk

Clock

Beyond

Supply

Voltage

Data

Beyond Ground

The transmission lines are defined with the following

parameters:

• Characteristic impedance, Z 0 (W)

• Propagation delay, D (ps/inch)

• Line propagation delay, t D (ps)

• Trace length, LENGTH (inches)

This list of variables can expand, depending on the PCB

design. For instance, a PCB design can have a backplane

with multiple transmission/receiver points. 3 All of the

transmission-line values depend on the particular PCB.

Typically, an FR-4 board’s Z 0 ranges from 50 to 75 W, and

D ranges from 140 to 180 ps/inch. The actual values of Z 0

and D depend on the actual transmission line’s material

Figure 3. Example single-ended transmission-line circuit

LENGTH

Transmitter

Receiver

Z t

0 , D

Z T

V T

V R

Z R

Output Impedance, Z T

Rise Time, t

Fall Time, t Rise

Fall

Characteristic Impedance, Z 0

Line Propagation Delay, t

Trace Length, LENGTH

PCB Construction:

Trace Inductance, L

Trace Capacitance, C

Input Impedance, Z R

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Data Acquisition

and physical dimensions. 4 The line propagation delay on a

particular board is calculated as

Figure 4. Basic cross sections of microstrip

and stripline boards

= ×

D LENGTH.

(1)

Microstrip

Stripline

For FR-4 boards, a reasonable propagation delay for a

stripline (see Figure 4) is 178 ps/inch, with a characteristic

impedance of 50 W. This can be verified on the board by

measuring the line inductance and capacitance of the trace

and inserting those values into the following equations:

Conductor

Reference Plane

Dielectric

D 10

(2)

Reference Plane

Conductor

(3)

D 85 ps/inch

e ,

corners of a device’s models are critical for creating an

accurate IBIS model. The silicon process varies from nomi-

nal to weak to strong models. The designer defines the

voltage settings from the component’s power-supply

requirements and varies them between nominal, minimum,

and maximum values. Finally, the temperature settings at

the component’s silicon junction are determined from the

component’s specified temperature range, the nominal

power dissipation, and the package’s junction-to-ambient

thermal resistance, or q JA .

Table 1 shows an example of the three PVT variables

and their relationships for a CMOS process with TI’s

ADS129x family of 24-bit biopotential-measurement ADCs.

These variables are used to perform the SPICE simulation

six times. The first and fourth simulations use the nominal

process models, the nominal power-supply voltage, and

the junction at room temperature. The second and fifth

simulations use the weak process models, a low power-

supply voltage, and a high junction temperature. The third

and sixth simulations use the strong process models, a

higher power-supply voltage, and a lower junction temper-

ature. The relationships between the PVT values map the

optimum corners for a CMOS process.

and

(4)

C TR is the trace line capacitance in farads/inch; L TR is the

trace line inductance in henrys/inch; 85 ps/inch is the

dielectric constant for air; and e r is the material dielectric

constant. For instance, if the microstrip-board line capaci-

tance is 2.6 pF/inch, and the line inductance is 6.4 nH/inch,

then D = 129 ps/inch and Z 0 = 49.4 W.

Lumped versus distributed circuits

Once the transmission lines have been defined, the next

step is to determine whether the circuit layout represents

a lumped or a distributed system. Generally, a lumped

circuit is small, and a distributed circuit requires much

more space on the board. A small circuit is one that has an

effective length (LENGTH) that is smaller than the fastest

electrical feature in the signal. To qualify as a lumped sys-

tem, the circuit on the PCB must meet the following

requirement:

Rise

LENGTH

(5)

Table 1. PVT simulation corners for ADS1296 IBIS model

POWER-

SUPPLY

VOLTAGE

(V)

where t Rise is the rise time in seconds.

With a lumped-circuit implementation on the PCB, ter-

mination strategies become a non-issue. Fundamentally, it

is assumed that the driver signals transmitted into the

transmission lines arrive at the receiver instantaneously.

Data organization in an IBIS model

An IBIS model includes data for three, six, or nine corners,

depending on the IC’s power-supply voltage range. The

variables governing these corners are the silicon process, 1

the power-supply voltage, and the junction temperature.

The specific process/voltage/temperature (PVT) SPICE

CORNER

NUMBER

SILICON

PROCESS*

TEMPERATURE

(°C)

Nominal

1.8

Weak

1.65

Strong

2.0

–40

Nominal

3.3

Weak

3.0

Strong

3.6

–40

*The standard for TI’s IBIS models is nominal = typical, weak = minimum, and

strong = maximum.

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Finding and/or calculating

transmitter specifications

The required transmitter speci-

fications for a signal-integrity

evaluation are the output

impedance (Z T ) and the rise

and fall times (t Rise and t Fall ,

respectively). Figure 5 shows

the package listing from the

IBIS model file, ads129x.ibs, 5

for TI’s ADS1296. The values

that are used to produce the

impedance are shown under the

“[Pin]” keyword and are also

within the buffer models (not

shown). The rise and fall times

are located in the transient por-

tions of the IBIS model’s data

listing.

Impedances of input and

output pins

The pin impedance of any

signal consists of the package

inductance and capacitance

added to the model’s imped-

ance. In Figure 5, the

keywords “[Component],”

“[Manufacturer],” and

“[Package]” describe a specific

package, a 64-pin PBGA (ZXG).

The package inductance and

capacitance for specific pins

can be found under the “[Pin]”

keyword. For instance, at pin

5E for the signal GPIO4, the

L_pin and C_pin values are

given. The L_pin (pin induc-

tance) and C_pin (pin capaci-

tance) values for this signal and

package are 1.4891 nH and

0.28001 pF, inclusive.

The second capacitance value

of interest is the silicon capaci-

tance, C_comp. The C_comp

values can be found under the

“[Model]” keyword in the model

DIO_33 listing from the

ads129x.ibs file (see Figure 6).

C_comp in this model is the

capacitance of the DIO buffer

with 3.3 V applied to the power-

supply pin. The “|” symbol indi-

cates a comment; so the active C_comp values in this list-

ing are 3.0727220e-12 F (typical), 2.3187130e-12 F (mini-

mum), and 3.8529520e-12 F (maximum), from which the

Figure 5. IBIS model’s package listing for ADS1296, including L_pin

and C_pin values

ads1296zxg :: PBGA, 64 pin package

[Component] ads1296zxg

[Manufacturer] TI

[Package] |ZXG (PBGA) - 64 pin

| variable typ min max

R_pkg 0.084959 0.084959 0.084959

L_pkg 1.726943nH 1.173300nH 2.802300nH

C_pkg 0.203317pF 0.155540pF 0.299270pF

[Pin] signal_name model_name R_pin L_pin C_pin

1A IN8P TERM 0.080388 1.4891nH 0.16542pF

1B IN7P TERM 0.078742 1.4385nH 0.15797pF

1C IN6P TERM 0.077541 1.4231nH 0.16358pF

5E GPIO4 DIO 0.106300 2.5339nH 0.28001pF

Figure 6. Model DIO_33 listing of C_comp values from ads129x.ibs file

[Model] DIO_33

Model_type I/O

|Signals SCLK, DAISY_IN

Vinl = 0.66

Vinh = 2.64

Vmeas = 1.65

Vref = 1.65

Cref = 15pF

Rref = 50

| typ min max

| (nom PVT) (fast PVT) (slow PVT)

C_comp 3.0727220e-12

2.3187130e-12 3.8529520e-12

|C_comp (ON state) 5.2856500e-12

4.3183460e-12 6.0694320e-12

|C_comp (OFF state) 6.2160260e-12

5.1916700e-12 7.4675830e-12

| Where nom PVT is Nominal Process, 3.3V, 27C

| Fast PVT is Strong Process, 3.6V, -40C

| Slow PVT is Weak Process, 3V, 85C

PCB designer can choose. During the design stage of the

PCB transmission lines, the typical value of 3.072722 pF is

an appropriate choice.

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Data Acquisition

Figure 7. Termination-correction strategy

MSP430 TM

ADS8326

R1 100

Clock

R4 100

Clock

C1 220 pF

R2 100

R5 100

C2 220 pF

R3 100

Data

R6 100

Data

C3 220 pF

The input and output impedances can be critical to

signal transmission. The following equation defines the

characteristic impedance of the IBIS model pins:

value for t Rise for the various transmission-line calculations

such as f Knee , f 3dB , and rising-edge lengths.

Using IBIS to design transmission lines

This article started out by discussing a PCB with mis-

matched termination impedances. The IBIS model was

then used to understand and find the critical elements for

this transmission problem. At this point, it is only fair to

show that there is a solution to this problem. Figure 7

shows the termination-correction strategy, and Figure 8

shows the corrected waveforms.

(6)

C_ pin C_ comp

Output rise and fall times

Across the industry, the convention for rise- and fall-time

specifications is to use the time needed for the output

signal to swing between 10% and 90% of the rail-to-rail

signal, which is usually 0 to DV DD . The IBIS Open Forum’s

definition for rise time is the same and was adopted

because of the long tails on CMOS switching waveforms.

Output, I/O, and three-state models within the IBIS

model have specifications embedded under the “[Ramp]”

keyword for R_load (test load), dV/dt_r (rise time), and

dV/dt_f (fall time). The range of the rise- and fall-time

data is from 20 to 80% of the voltage-output signal. If the

denominator of the typical dV/dt_r values is multiplied

by 0.8/0.6, the rise-time value will change from a 20-to-

80% swing to a 10-to-90% swing. Please note that the

data represents a buffer with the resistive load, R_load.

In the ads129x.ibs file, DIO_33 data assumes a 50-W

load, so the data does not extend to DV DD . The resulting

number from this calculation will provide an appropriate

Figure 8. Stable signals from termination correction

Channel 1 Clock

Channel 2 Data

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